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1 September 1991 Holographic optical backplane hardware implementation for parallel and distributed processors
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A working model of an optical backplane has been built to demonstrate the feasibility of incorporating free space, multifaceted and angularly-multiplexed, holographic interconnect technology to enhance the electronic processing architecture. This new design will allow special configurations for parallel and distributed processing and can be made compatible with standard electrical bus connections. The current demonstrator unit contains four transceiver boards in a standard 19 in. rack-mount chassis. It can support bidirectional 125 MHz transmission per channel with a loss budget (allowable optical attenuation) of 30 dB for large fan-out (> 20 boards). Interconnection holograms have been designed to compensate for the large wavelength drift of laser diodes expected to be the result of temperature fluctuations in the processor box. The design also allows a large mechanical tolerance for board misalignment and vibration. Multiple interconnection patterns, each set representing a particular architecture, can be recorded on a single substrate to provide reconfiguration. The proposed holo-backplane can interconnect multiple transmitters and/or receivers (each could support different logic and/or signal levels) per board to realize truly flexible processing schemes.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Richard C. Kim and Freddie Shing-Hong Lin "Holographic optical backplane hardware implementation for parallel and distributed processors", Proc. SPIE 1474, Optical Technology for Signal Processing Systems, (1 September 1991);


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