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1 August 1991 Algorithms and architectures for implementing large-velocity filter banks
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Abstract
The velocity filter (or 3-D matched filter) is known to be a powerful signal processing technique for detecting and tracking weak moving objects in electro-optical image sequences. To date, however, its application has been limited by the enormous amounts of hardware required to implement the large 'filter banks' that are needed to cover the prior uncertainty in apparent target velocity. This paper presents the results of an algorithm and architecture study that explored ways of significantly reducing the real-time hardware required to obtain a specified level of performance with the velocity filter approach. The most effective solution, based on an optimum single-bit velocity filter implemented in a special-purpose bit serial processor, is capable of achieving extremely high filter computation rates on a single semi- custom VLSI chip. A real-time brassboard implementation of this architecture, the Velocity Filter Processor, is currently under development at Space Computer Corporation.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Alan D. Stocker and Preben D. Jensen "Algorithms and architectures for implementing large-velocity filter banks", Proc. SPIE 1481, Signal and Data Processing of Small Targets 1991, (1 August 1991); https://doi.org/10.1117/12.45650
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