1 August 1991 Integrated processor architecture for multisensor signal processing
Author Affiliations +
Proceedings Volume 1481, Signal and Data Processing of Small Targets 1991; (1991); doi: 10.1117/12.45678
Event: Orlando '91, 1991, Orlando, FL, United States
Sensor systems being conceived and fabricated today have high processor content and tend to be software intensive. Recent advances in hardware technology have made possible the implementation of complex high-performance multisensor algorithms. Hardware capability alone is not sufficient to ensure the successful implementation of these software intensive systems. In addition, it is necessary to carefully structure the processing system to ensure that high-performance multisensor algorithms can be implemented. Traditionally, implementability has meant throughput and memory capacity. This paper extends implementability to include the ability of a processing system architecture to support efficient integration and test. This is particularly important when the implicit requirements of cost and schedule are considered. To illustrate processor architecture impact on integration and test, an example from the LOWKATER program is examined. This was an extremely complex multisensor processor containing a digital laser radar receiver, a passive sensor target detector, and a digital controller for the beam pointing system. Architectural alternatives are presented and the selected architecture is examined in detail.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Robert E. Nasburg, Steve M. Stillman, M. T. Nguyen, "Integrated processor architecture for multisensor signal processing", Proc. SPIE 1481, Signal and Data Processing of Small Targets 1991, (1 August 1991); doi: 10.1117/12.45678; https://doi.org/10.1117/12.45678

Signal processing

Digital signal processing


Data processing

Control systems

Data conversion

Computer architecture


32b RISC/DSP media processor: MediaDSP3201
Proceedings of SPIE (March 08 2005)
Parallel processor for real-time structural control
Proceedings of SPIE (July 22 1993)
DSP array for real-time adaptive sidelobe cancellation
Proceedings of SPIE (December 01 1991)
Controlling the autonomy of a reconnaissance robot
Proceedings of SPIE (September 02 2004)

Back to Top