GaAs optoelectronic integrated circuits (OEICs) require the combination of several types of devices that place widely differing demands upon the layer structure and processing technologies. We report on the development of MESFETs, bipolar transistors, detectors, and a unique class of beam-steered facetless grating surface-emitting lasers and the integration of up to 300 devices of multiple types.

Epitaxial liftoff permits the integration of III-V films and devices onto arbitrary material substrates. This paper will review Bellcore's work on opto-electronic integration of III-V optical transmitter and receiver devices onto LiNbO3, glass, Silicon and sapphire substrates.

An optoelectronic integrated circuit (OEIC) suitable for applications requiring highly parallel optical interconnections has been designed, fabricated and demonstrated. The chip integrates optical emitters, optical detectors and GaAs based electronic I.C.s on the same substrate. Its architecture consists of a two-dimensional 8x8 array of cells, with each cell containing a double heterojunction Light Emitting Diode (LED), a lateral ionimplanted photoconducting detector (PD), and a GaAs Metal-Semiconductor Field Effect Transistor (MESFET) circuit which performs amplification of the detector signal, thresholding, memory and LED drive functions. The chip consists of a total of 1300 FETs, 64 LEDs, 64 photodetectors and 500 thin-film resistors. Discrete devices fabricated with the integrated process have performance characteristics similar to those of non-integrated devices. The electrical and optical functionality of 8x8 arrays has been demonstrated. However, a feedback problem has been shown to exist between the LEDs and LED driver FETs. The source of this problem is discussed.

Diamond's thermal, mechanical, chemical, electrical and optical properties are ideally suited to the requirements of multichip modules. Gigahertz clock rates and increased device density are facilitated using diamond as a base material and as a hermetic passivation layer. Three dimensional architectures with optical communications would allow high speed communications for advanced designs in computers and rugged electronics. This paper provides an overview of potential applications and advantages of Diamond Multichip Modules.

Vertical cavity surface emitting lasers (SELs) offer many desirable features that are suitable for applications in optical interconnect, optical signal processing and optical computing. We describe a GaAs vertical cavity SEL with a novel structure, and discuss those key laser performance characteristics such as threshold current, power output, efficiency, far field divergence, and modulation response that are important to these potential applications.

Fiber-optic switching systems typically exhibit large losses associated with splitting and combining of the optical power, and with excess component losses. These losses increase quickly with switch size. To obtain acceptable signal-to-noise performance through large optical switching, optical amplifiers can be used. In applications requiring optical switching, semiconductor optical amplifiers (SOAs) are preferred over erbium-doped fiber amplifiers due to their fast switching speeds and the possibility of their integration in monolithic structures with passive waveguides and electronics. We present a general analysis of optical switching systems utilizing SOAs. These systems, in which the gain provided by SOAs is distributed throughout the optical system, are referred to as distributed optical gain (DOG) systems. Our model predicts the performance and achievable sizes of switches based on the matrix-vector multiplier crossbar and Benes network. It is found that for realistic SOA parameters, optical switches accommodating extremely large numbers of nodes are, in principle, achievable.

Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC Spatial Light Modulators (SLMs) can provide a unique and innovative solution to these issues. This paper will report the motivations for the system, describe the major areas of architectural requirements, discuss interconnection topologies and processor element alternatives, and document an optical arbitration (i.e., control) scheme using 'smart' SLMs and optical logic gates. The network topology is given in Section 2.1 Architectural Requirements - Networks, but it should be noted that the emphasis is on the optical control scheme (Section 2.4) and the SYSTEM.

Sorting is central to the solution of many knowledge—based and switching problems in advanced compiting and carrriunications systems . The combination of compare-and-exchange modules with perfect-shuffle interconnections can carry ou piplmed bitonic sorting networks . In this paper , compare-and-exchange switches are impleitnted by using bistable light emitting diode (BILED) circuits. The comparison is perforrd by the latching logic devices, and exchange unit forms a crossbar switch dependent on the results of the comparison . Compare-and-exchange switches based on BILED circuits have many features , such as low power consumption, wide range of input wavelength and compatible with the current optoelectronic integration circuits (OEIC's) technology.

In computing, trends toward parallel processing, multiprocessor computers, higher operating speeds, and larger as well as denser very large scale integrated (VLSI) circuits have provided an impetus for the development of advanced interconnection technology.

Many researchers have propsed free-space optical interconnects as an alternative to electrical and optical guided wave techniques for connecting electronic or optical processors1,2. However little discussion has been given to problems associated with system packaging. This presentation provides an overview of several important issues in yjis area which must be solved prior to realizing free-space optical interconnect systems.

We examine the optical limits on the packing density of free-space optical interconnection networks. We investigate this question by using a particular free-space perfect shuffle architecture implemented with simple lenses, shown in Fig. 1.

This paper discusses the design of binary holograms producing weighted coupling between planes of single mode devices. Theoretical results are reported on the coupling of single mode devices in terms of an expansion of the hologram outputs into distinct diffractive sidelobes. In this formalism, the coupling efficiency between two devices is given by the product of the fan-out and fan-in efficiencies of the respective transmitting and receiving holograms. It is shown how the simulated annealing algorithm can be used to produce binary holograms with the desired coupling properties. Computational and experimental results demonstrate the effectiveness of the method.

We explore the ability of a Double Phase Conjugate Mirror (DPCM) to compensate for thermal, vibrational and other environmental fluctuations. This property lends itself to the establishment and maintenance of bidirectional optical interconnections. We further introduce a bidirectional interconnection scheme that utilizes two wavelengths.

We discuss our cascaded correlator-based optical numeric processor and its projected performance (our goal is a numeric processor and not a general-purpose optical processor). We use symbolic substitution (for parallelism on long words and arrays of words), the modified signed-digit number representation (for speed, i.e. reduced carries), and a new encoding and substitution architecture to improve performance.

Many ideas on opto-electronic realizations of various neural networks have been described over the last few years. Most of them use analog optical devices and have been shown to work satisfactorily as simple content addressable memories. An important question is how much of the faults and defects in the storage and retrieval systems, that is, the spatial and temporal errors in the spatial light modulators or the photorefractive arrays and the detector arrays these neural network realizations can tolerate. One measure of fault tolerance is the probability of correct retrieval or classification when the network is used as a content addressable memory. Using recent theories we will derive upper bounds to the probability of errors in various popular opto-electronic neural network realizations as a function of the size, capacity, and the magnitude of spatial and temporal errors. Guidelines on the design and implementations of opto-electronic neural networks will be derived.

Electro-optic (EO) polymers have emerged as a new class of materials for integrated optics and lightwave device applications. We provide a concise engineering description of the state of EO polymer materials development and then introduce their application to switchable, guided wave optical interconnections. Such interconnections potentially offer higher routing density, lower noise, lower propagation delay, and the simplification of many problems encountered in the design of high-frequency on- and off-module connections for high-performance electronic systems.

The term "photoneuron" describes an electro—optic hardware element which permits an optical implementation of the postulated information transfer processes of the neurons in the human brain. The photoneuron provides a dynamic activation and control mechanism for highly parallel computers and permits immediate implementation of reconfigurable high speed optical interconnects. The suggested method for interconnecting processors in a photoneuronic network consists of embedded optical fibers in composite materials to form optical backplanes utilizing "smart skin" technology. This method eliminates the environmental concerns and technological barriers posed by free space optics and integrated optics, while providing a sound engineering approach leading to the all optical computer. This paper briefly reviews the physiological activity of neurons in the human brain. Optical analogies for processor activation in neural networks corresponding to the nerve impulse activation in the brain are then described. The paper then suggests the utilization of optical signal parameters and encoding to emulate the information exchange of neurotransmitters provided by first and second messenger molecular activity across the synaptic "connections" of neurons in the brain. This represents a departure from most neural networks which dwell on threshold processor activation and ignore the exceedingly complex molecular information exchange mechanisms of the brain. Digital, analog, and combinatorial alternatives are described.

The progress in parallel processing technology in recent years has resulted in increased requirements to process large amounts of data in real time. The massively parallel architectures proposed for these applications require the use of a high speed interconnect system to achieve processor-to-processor connectivity without incurring excessive delays. The characteristics of optical components permit high speed operation while the non-conductive nature of the optical medium eliminates ground loop and transmission line problems normally associated with a conductive medium. The MITRE Corp. is evaluating an optical wavelength division multiple access interconnect network design to improve interconnectivity within parallel processor systems and to allow reconfigurability of processor communication paths. This paper will describe the architecture and control of and will highlight results from an 8-channel multi-processor prototype with effective throughput of 3.2 Gigabits per second (Gbps).

An optical crossbar for single-mode fibers using acoustooptic (AO) interactions in a single acoustooptic device capable of rapid reconfiguration is presented.

We discuss our motivation in determining the use of optics in a general purpose parallel computing system when examined from the point of view of Computer Architecture. We assume the use of traditional electronic nodes interconnected via optical waveguides. We define Distributed Shared Memory (DSM) and describe our optical interconnection network architecture by defining our proposed architectural environment and optical bus access control protocols. We present some analytical performance metrics and describe our ongoing simulation studies. We believe our architecture shows promise in allowing a large number of nodes to be optically interconnected in a familiar topology.

Multimode stripe waveguides for optical interconnections in signal processors were fabricated in BGG3 1-glass and in 6F44-polyimide. The fabrication technologies were field assisted ion exchange for waveguides in glass and spin coating followed by dry etching for polymeric waveguides. The waveguide dimensions were between 20 and 30 µm for the height and between 30 and 40 m for the width. The attenuation was found to be 0. 1 dB/cm in glass and 0.8 dB/cm in polyimide. Bends and intersections have been characterized.

Three dimensional optical memory devices may be designed to operate by means of two photon interaction in a solid matrix. Photochromic materials have been used in volume memory writing and reading with some success. The information density, cycle times and stability are some of he parameters addressed in this paper.

In this paper, auto—, hetero—associative memory of 2—D Hopfield model [1] described in terms of quasi—inner—product are realized by using multi—imaging and correlation hybrid system, respectively.

OptiComp is currently completing a 32 -bit, fully programmable digital optical computer (DOC II) which is designed to operate in a UNIX environment running RISC microcode. OptiComp's DOC II architecture is focused toward parallel microcode implementation where data is mputin a dual railformat. By exploiting thephysicaiprincipals inherent to optics (speed and low power consumption), an architectural balance of optical interconnects and software code efficiency can be achieved including high fan-in and fan-ouL OptiComp's DOC II program is jointly sponsored by the Office of Naval Research (ONR), the Strategic Defense Initiative Office (SDIO), NASA space station group and Rome Laboratory (USAF). The following companies mentioned will presentpapers following SPW code 1563-28 describing in detail the sub components forDOC II. OptiComphas contracted Harris Corporation to build and to deliver the 64 channel acousto-optic spatial light modulators, Spectra DiodeLaboratones to build and to deliver an 8 element index guided laser diode bars capable of producing in excess ofone watt Th at 830nm, Optics 1 Inc. to optimize and to fabricate the optical components ( i.e. collimation and relay optics) and EG&G to develop a 128 element high speed APD array. This paper not only describes the motivational basis behind DOC II but also provides an optical overview and architectural summary of the device, which will allow the emulation of any digital instruction set.

We demonstrate both common electrode and addressable arrays of single mode semiconductor lasers suitable for optical computing and optical data storage. In the common electrode geometry, eight lasers have been fabricated on a single chip which show excellent spectral and power uniformity. Total optical power obtained from this array has been in excess of 1.2 Watts CW. We have also fabricated two and nine element monolithic, individually addressable arrays with emitter spacings between 10 jim and 150 p m. Separately addressed, each element emits in a single spatial mode to greater than 0.1 Watts. For the nine element array, uniformity of better than 1.0 nanometer in wavelength and 1 milliamp in operating current across the array has been obtained. Results on crosstalk and reliability of the arrays are presented.

Matrix - matrix and matrix - vector multiplications can be performed optically using techniques involving a number of spatial light modulator technologies. Acousto-optic modulators offer the advantages of high efficiency and fast reconfiguration times, on the order of several nanoseconds. Recent efforts to reduce the package size of the acousto-optic SLM devices and increase their pertormance characteristics have rendered this approach more attractive to system designers. This paper reports the results of such efforts applied to a 64 channel acousto-optic modulator and a 64 channel acousto-optic deflector that can be used in tandem to optically compute matrix-matrix and matrix-vector calculations. The modulator is placed in the optical path prior to the deflector and is used as the column selector. The deflector can be operated by pulsing the RF signals to produces packets of information along the optical aperture and reimaging the deflector at the detector plane. This method known as Scophony imaging performs the function of row selector and allows true two-dimensional SLM operation from the acousto-optic devices. Specification trade-offs and fabrication issues are covered. Measured performance parameters are summarized.

A high speed 128-element linear avalanche photodiode array, suitable for use in optical computing applications, has been designed and fabricated. The use of a guard ring surrounding the array results in low dark current and noise in the individual elements. Operation at gain I 00 has shown good APD performance, with element dark currents less than 3 nA, noise less than 0.1 pNHz1', and rise and fall times about 1 ns. The design of the device makes it suitable for operation at frequencies up to 200 MHz. A solder bump mounting technique, and multi-layer substrate design are described which minimize capacitance between the elements, thereby maintaining low crosstalk. For further reduction of crosstalk, an alternative chip design is described, in which a guard ring runs between all the elements.

OptiComp Corporation is developing a general purpose digital optical computer which makes use of commercially available component technology. This computer has been named DOC II. In this manuscript, we briefly discuss some of the issues relating to the optical system of DOC II. We discuss the optical design of the various subsystems, the opto-mechanical design, and the simple system evaluation tests that were performed. As part of this discussion, we reveal some of the driving specifications, tolerance issues, and show actual test data for some of the optical subsystems.

The OptiComp DOC II processor serves as the basis for the design of a hybrid optical/electronic architecture that solves systems of linear equations using Gaussian elimination. The architecture consists of a cascade of acoustooptic modulator based programmable logic arrays (PLAs) operating at a rate of 100MHz. Arithmetic operations are performed using 16-bit fixed point arithmetic, and include subtraction, multiplication and division. The design goal is to solve a system of linear equations in 10 unknowns in under 20 µs, for a target application of null steering for phased array radar. The design goal is achieved with reasonable complexity.

This paper describes current electronic hardware subsystems and software code which support OptiComp's 32-bit general purpose digitaloptical computer (DOC II). Thereaderisreferredtoearlierpaperspresentedin this session forathrough discussion of theory and application regarding DOC II. The primary opto-electronic subsystems include the drive electronics for the multichannel acousto-optic modulators, the avalanche photodiode amplifier as wellas threshold circuitry and the memory subsystems. This device utilizes a single optical Boolean vector matrix multiplier and it's VME based host controller interface in performing various higher level primitives. OptiComp Corporation wishes to acknowledge the fmancial support of the Office of Naval Research, the National Aeronautics and Space Administration, the Rome Air Development Center and the Strategic Defense Initiative Office for the funding of this program under contracts N00014-87-C-0077, N00014-89-C-0266 and N00014-89-C- 0225.

Paralleloptical interconnects have been well documented [1,2]. The theoiy ofparallel optical interconnects is the basis forOptiComp's current digital optical computer (DOC) II design and fabrication program. This paperwiidemonstrate a natural extension of the parallel theory into global or 3-dimensional theory where a single point is imaged to every other interconnect point. This paper will introduce an algorithm for a digital optical computation concept and will discuss the hardware architecture for extremely wide word (~128 bits) single clock addition, which is based on global free space optical interconnections. In addition, energy consumption and throughput efficiency of the new adder will be examined. The motivational basis for the utilization of global free space optical interconnects is documented in reference 3.