Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree

Naofumi Takagi

doi:10.1117/12.49825

1 December 1991 Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree

Naofumi Takagi

Proceedings Volume 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II; (1991) https://doi.org/10.1117/12.49825
Event: San Diego, '91, 1991, San Diego, CA, United States

Abstract

An arithmetic unit based on a high-speed multiplier with a redundant binary addition tree is proposed. It is efficient for numerical computations with iteration of multiplications and addition/subtractions. A new multiplier recoding method makes the arithmetic unit efficient for these computations.

Citation Download Citation

Naofumi Takagi "Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree", Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); https://doi.org/10.1117/12.49825

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