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1 December 1991 DSP array for real-time adaptive sidelobe cancellation
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A programmable, reconfigurable DSP array has been designed in response to the need for a real-time adaptive sidelobe canceller to support wide bandwidth high frequency radar concepts. These concepts incorporate multiple (up to 128) mainbeams and many degrees of freedom using many auxiliary antenna elements, and employ frequency sub-banding to partition a 1 MHz instantaneous bandwidth. The real-time sidelobe canceller is based on the Gram-Schmidt orthogonalization procedure and uses concurrent block adaptation to derive an optimal solution for the available data. The sidelobe canceller implementation configures the modular DSP array into a two-dimensional Gram-Schmidt processor. A proof-of-concept sidelobe canceller implementation will provide the capability to perform sidelobe cancellation on two simultaneous mainbeams using eight auxiliary channels. The DSP array sidelobe canceller can be expanded to support more than 128 mainbeams using auxiliary channels. The array consists of TMS320C30 based processing nodes providing four independent data ports (two inputs and two outputs) connected via high speed serial data links supporting two megawords-per-second sustained throughput rates (8 megawords-per-second burst rates). These manually configured data connections are separated from the control structure, allowing a variety of interconnect strategies (one-dimensional, two-dimensional, etc.). A host processor is used to download application code and control the system. This programmable, reconfigurable array processor can also be used for a variety of other applications including the singular value decomposition, matrix-matrix multipliers, and FFTs.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Terry L. Rorabaugh, John J. Vaccaro, Kevin H. Grace, and Eric K. Pauer "DSP array for real-time adaptive sidelobe cancellation", Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991);


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