1 December 1991 Naval Research Laboratory flex processor for radar signal processing
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Abstract
This paper describes a programmable radar signal processor architecture developed at the Naval Research Laboratory (NRL). The design incorporates T.I. TMS320C30 programmable digital signal processor devices, Xilinx programmable gate arrays, TRW FFT devices, and a parallel array of Inmos Transputer microprocessors. The architecture is extremely flexible and is applicable to a wide variety of applications.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James J. Alter, James B. Evins, and J. P. Letellier "Naval Research Laboratory flex processor for radar signal processing", Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); doi: 10.1117/12.49831; https://doi.org/10.1117/12.49831
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