A first-principles low-order model of rapid thermal processing ofsemiconductor wafers is derived. The nonlinear model describes the steady-state and transient thermal behavior of a wafer with approximate spatial temperature uniformity undergoing rapid heating and cooling in a multilamp RTP chamber. The model is verified experimentally for a range of operating temperatures from 400°C to 900°C and pressure of 1 torr in an inert N2 environment. Advantages of the low-order model over detailed models include ease of identification and implementation for real-time predictive applications in signal processing and temperature control. This physics-based model is used in the design of an advanced real-time multivariable control strategy. The strategy employed a feedforward mechanism to predict temperature transients and a feedback mechanism to correct for errors in the prediction. The controller is applied to achieve a ramp from 20°C to 900°C at a rate of 45°C/second in a one atmosphere environment with less than 15°C nonuniformity during the ramp and less than 1°C average nonuniformity during the hold as measured by three thermocouples.

Issues of rapid thermal processing (RTP) system design and process applications are reviewed. Temperature measurement is the most important and limiting factor in current RTP systems. Problems related to the temperature measurement and control and potential solutions are discussed. Process uniformity control is another important issue in RTP system design. Reactor chamber design, selection and arrangement of heat source, as well as issues related to dislocation generation, patterned and doped wafer, and ramp-up (down) thennal cycle are considered. Experimental results (RTO, RTCVD silicon nitride and polysilicon) based on an in-house RTP system developed in our laboratory are taken as examples to demonstrate the process applications and system requirements for single wafer processing.

Future DRAM devices require higher performance dielectrics for which novel process chemistries must be studied. Nitrous oxide (N20) has shown promising results as a process gas for rapid thermal oxidation. However, current practice in rapid thermal processing (RTP) has neglected the effect of process gas on temperature control. For N20, this results in a large temperature offset and oscillation, and poor thickness uniformity. Evidence is presented indicating that gas-phase absorption of the pyrometer signal produces the difficulties observed when using N20. These difficulties do not occur if the pyrometer is operated at a wavelength not absorbed by the N20. This behavior also does not occur when using 02 as the process gas since it is transparent at the pyrometer wavelengths used. The data shows that one must examine the absorption spectra of the process gas for compatibility with the pyrometer wavelength used for temperature measurements.

Modem statistical modeling techniques are applied to the characterization and optimization of Rapid Thermal Chemical Vapor Deposition. The problems of deposition during process ramps and thickness uniformity modeling wafer are addressed. A two-phase fractional factorial experimental design is used to generate models for the deposition rate, uniformity measures, and normalized time responses. A constrained algebraic optimization algorithm is used to find the optimum settings for the reactor for the deposition of 2000A of polysilicon. The methods that are developed to handle these problems are shown in an application to the deposition of polysilicon in a LeiskTM reactor.

A novel dual color pyrometry method forcorrecting wafer-to-waferemissivity changes during rapid thermal processing (RiP) is discussed. This new technique, using a system called TRAC (Temperature Repeatability with Automatic Control) addresses a key issue affecting the reproducibility of RTP production applications: accurate temperature measurement and control. The effect of this new emissivity correction method on reproducibility ofrapid thermal oxidation (RTO) and ion implant rapid thermal activation (RTA) of wafers with varying emissivities is presented. The results demonstrate significant improvement oftemperature control and temperature repeatability from wafer-to-wafer both for RTO and short RTA processes when in situ emissivity correction is applied.

Fast and accurate non-contacting temperature measurements are possible with a new approach which offers significant advantages over optical pyrometry. By using laser extensometry to measure in-plane thermal expansion, the temperature of silicon wafers can be determined during rapid thermal processing to better than 0.5 °C accuracy from room temperature to more than 1300 °C. This approach is entirely non-contacting and works on wafer surfaces exactly as they are, with no need for calibration procedures or emissivity determinations. Its 0 1 °C resolution and rapid response make it well-suited for dosed loop control of rapid thermal processing. In addition, this measurement concept lends itself well to compact packaging at low cost.

We report in this work the application of the Surface Charge Analysis (SCA) technique for in-line process control and characterization of re-oxidized nitrided oxide (ONO) films processed by RiP. Film samples with a wide variety of processing conditions have been fabricated and characterized using the SCA technique. Following SCA characterization, electrodes were formed on the samples followed by detailed CV measurements. Finally, correlations between SCA and CV determined parameters were established. Since the SCA is an optical technique which is non-invasive and requires no electrode processing, and some degree of correlation was found between the two techniques, this suggests that the SCA warrants further investigation as a technique for in-line process control and characterization for RTP grown ONO films.

This paper will continue a review of the presently available whole-wafer mapping techniques and discuss their applicability to uniformity characterization of various rapid thermal processor (RTP) thin films. These techniques include spectral analysis, beam profile reflectometry, modulatedoptical reflectance, Fourier Transform Infrared Spectrometry (FTIR), four-point probe, reflective-optical inspection, x-ray topography (XRT), wafer flatness and stress. Selected contour and uniformity maps resulting from analysis of rapid thermal oxidation (modulated-optical reflectance, wafer thickness and stress measurements) and epi-silicon (reflective-optical inspection) RTP thin films will be presented. Comparisons between two different thin film thickness measurement technologies will be discussed

Processing and materials issues for the fabrication of Si/Sii_Ge/Si heterojunction bipolar transistors (HBTs) are discussed, particularly as they relate to the use of rapid thermal processing techniques. The addition of Ge to the base of the bipolar transistor provides the ability to tailor the bandgap throughout the device for optimum performance. However, these devices pose several challenging process integration issues. The sensitivity of device performance to temperature-time exposure originates from fundamental processes such as islanding during growth and annealing, impurity incorporation in Sii_Ge, dopant diffusion in and from Sii_Ge layers, and the formation of misfit dislocations. Each of these issues sets constraints on processing variables such as temperature, time, and ambient purity, and on device design parameters such as Ge and dopant depth profiles. Rapid thermal processing techniques may offer advantages in several of these areas.

Through proper reactor design and accurate temperature measurement, high quality silicon/silicon-germanium alloy (Si1-xGex) strained layer structures can be grown by Rapid Thermal Chemical Vapor Deposition with growth temperatures in the 600-700 ° C range. Photoluminescence measurements show well resolved band-edge features, indicating that the films are of very high quality. Quantum confinement effects have also been observed in quantum wells with widths down to 3 nm.

The device characteristics of n-p-n poly-emitter bipolar transistors under a variety of interface control schemes have been studied. Common emitter current gain, reverse bias emitter/base leakage current and emitter resistance parameters have been measured. Polysilicon emitter contacts were deposited in a RTCVD reactor, with and without an in-situ interface treatment step, using SiH IH2 chemistry at 4 torr total pressure. Further, the effect of a 30:1 HF dip, prior to loading the wafers into the load-lock, was also investigated. It is concluded that the behavior of the NPN transistors has a direct correlation with the polysilicon microstructure and interfacial oxide layer which is primarily influenced by the interface treatment process. The highest current gain and lowest emitter/base leakage current was obtained for the samples with a cleaned/oxidized polysilicon/silicon interface.

Rapid thermal annealing (RTA) yields improved electrical activation and carrier mobility compared to conventional furnace annealing (FA) in III-V compounds. This paper reviews the results of our RTA work on indium based compounds. Studies on InP, InGaAs, and InSb implanted with various species at room and elevated temperatures are presented. The RTAs were performed using a halogen lamp station for InP and InGaAs, and a metal strip heater for InSb, using dielectric and proximity caps. Donor electrical activations close to 100 % were obtained for 875°C/10 s RTA on Si implanted InP:Fe for ion energies up to 20 MeV and for doses which do not make the material amorphous. RBS measurements on the annealed material indicated an effective removal of the implant damage. The RTA on Be/P and Be/ Ar coimplanted InP:Fe yielded acceptor Be electrical activations of 80 % without Be in-diffusion. The RTA on Ge implanted InP:Fe gave a maximum donor activation of 50 %. For low-energy Si and Be/P implantations into In0.53 Ga0.47 As, the results are similar to those of InP. The RTA performed on transition metal (Fe, Cr, and V) implanted InGaAs has resulted in the diffusion of the dopant and formation of multiple peaks in the implant profile. Only Fe implantation gave highly resistive regions in n-type InGaAs. Light ion (H, He, B) bombardment on p-type InGaAs gave resistivities close to the intrinsic limit which are stable up to a maximum processing temperature of 350 °C. RTA on Be implanted InSb grown on GaAs gave p-type activation as high as 89 %. Sulphur implantation in InSb yielded a maximum of only 16 % donor activation even for anneals at 510 °C, which is close to the melting point temperature of InSb. Silicon implant showed amphoteric behavior in InSb.

In this study, damage induced by Ar+ and Si+ ion implantation and its annealing behavior during rapid thermal annealing for 10 sec at temperatures between 575-1100°C were investigated by thermal wave modulated optical reflectance, deep level transient spectroscopy, reflection high energy electron diffraction, Rutherford backscattering aligned spectra and transmission electron microscopy. Our data show that (1) thermal wave signal and its variation with repect to rapid thermal anneal temperature strongly depend upon implant dose and anneal temperature; (2) both implant species induce four distinctive deep trap levels; (3) these traps evolve during rapid thermal annealing!; and (4) for the single Si+ ion implanted samples, the variation of total trap concentration with respect to rapid thermal anneal temperatures follows that of TW. However, in the case of Ar+ ion implanted samples, no apparent correlation between thermal wave signal and DLTS trap condition could be made.

Twelve rapid thermal processes have been developed for over fifteen critical thermal fabrication steps in a sub-0.50 p.m CMOS technology. These processes include dielectric growth (dry and wet rapid thermal oxidations), thermal anneals (source/drain & gate anneals, CMOS well formation, TiN/TiSi2 react, and forming gas anneal), rapid thermal chemical-vapor deposition (amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride), and in-situ dry cleaning. The pro­ cess temperature range of these rapid thermal processing fabrication steps extends between 400°C and 1100°C. Complete sub-0.50 p.m CMOS process integration has been successfully demonstrated in a single-wafer minifactory consisting of all-RTP/no-furnace thermal processing.

At Dow Corning Corporation, hydrogen silsesquioxane, (HSi03/2)n. is being commercialized as a precursor to silica coatings for applications in the protection of electronic devices and as an interlayer dielectric layer in the fabrication of integrated circuits. Rapid Thermal Processing (RTP) has been used to convert hydrogen silsesquioxane to silica at temperatures as low as 400 °C with minimal to no adverse effects to temperature sensitive integrated circuits. The resulting silica films had lower mechanical stress and better chemical homogeneity than films processed in a conventional furnace using the same precursor and temperatures. Two different RTP units, one employing an arc lamp and the other with tungsten-halogen lamps, gave comparable results.

The use of Si02 gate oxides with thicknesses of <100A will put stringent requirements on the control of contamination during device manufacturing. It has been realized only recently that control of molecular contamination is as important for critical device films as control of particulates. We present in this paper an investigation of challenges of thin gate oxides, possible alternative oxide deposition schemes, and control of foreign molecular species. using an ultra-clean, integrated processing system with in-situ analysis capabilities. In particular, the interfacial region of thermal gate oxides is investigated, as well as the chemical vapor deposition of oxides from SiH4 and 02 , and the incorporation of fluorine into gate oxides.

A comprehensive review of chemical composition and electrical properties is presented for thin gate oxides with small amounts of nitrogen or fluorine, incorporated by rapid thermal processing. Electrical properties of these chemically modified oxides are correlated with the changes in chemical composition and the resulting structural modifications. Qualitative models described in some of the earlier works are used to establish these correlations. It is concluded that the changes in chemical composition of Si02 can be controlled to realize superior gate dielectrics for application in ULSI MOS devices.

Considerable attention has been focused on the development of ultrathin insulators for use in the IC industry. In particular, solid-state sensors require physically durable and electrically suitable materials. One possible choice is silicon nitride: an excellent diffusion barrier, physically rugged, and a suitable insulator. For most thin film applications, CVD silicon nitride is the preferred material; however, it is difficult to deposit ultrathin layers (<50A). Thus, RIP thermal nitridation of silicon was investigated as an alternative to CVD silicon nitride for IC sensor applications. Ultrathin silicon nitride films have been thermally grown in ammonia and nitrogen ambients by rapid thermal processing. The effects of several variables on the growth of thermal nitride and its material properties were evaluated electrically (1-V behavior) and physically (etch resistance to HF). Some conditions gave the expected results: longer nitridation times and higher nitridation temperatures (generally) improved nitride properties. Other variables gave mixed results, improving physical resistance at the expense of electrical properties (annealing, two-step nitridation, in situ gaseous cleaning} or vice-versa (extended purges, low-pressure nitridation). By varying these process parameters, a film with an etch rate of 2.64 Atmin and a second film with a field strength of 8.16 MV/cm (to pass 1 uA through a 104 ul'f12 structure} were achieved. However, the single film with the best overall physical and electrical properties had an etch rate of 3.66 Atmin in 5:1 BHF, required a field of MV/cm, and maintained a current density of 0.12 mA/cm2 at -1 V