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1 February 1992 RTP for advanced CMOS process integration
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Proceedings Volume 1595, Rapid Thermal and Integrated Processing; (1992)
Event: Microelectronic Processing Integration, 1991, San Jose, CA, United States
Twelve rapid thermal processes have been developed for over fifteen critical thermal fabrication steps in a sub-0.50 p.m CMOS technology. These processes include dielectric growth (dry and wet rapid thermal oxidations), thermal anneals (source/drain & gate anneals, CMOS well formation, TiN/TiSi2 react, and forming gas anneal), rapid thermal chemical-vapor deposition (amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride), and in-situ dry cleaning. The pro­ cess temperature range of these rapid thermal processing fabrication steps extends between 400°C and 1100°C. Complete sub-0.50 p.m CMOS process integration has been successfully demonstrated in a single-wafer minifactory consisting of all-RTP/no-furnace thermal processing.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mehrdad M. Moslehi, John Kuehne, Lino Velo, David Yin, Dick Yeakley, Steve S.H. Huang, Rhett Barry Jucha, and Terence Breedijk "RTP for advanced CMOS process integration", Proc. SPIE 1595, Rapid Thermal and Integrated Processing, (1 February 1992);


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