Translator Disclaimer
1 November 1991 VLSI implementation of a buffer, universal quantizer, and frame-rate-control processor
Author Affiliations +
Abstract
The CCITT Recommendation H.261 [1] describes the video coding and decoding method for the moving picture component of audiovisual services at the rates of px64 kbit/s, where p is in the range 1 to 30. Accordingly, several chip sets realizing these methods have been announced[3,4,5,6]. In this paper, a new architecture and implementation of an adaptive coding controller chip is reported. The main features of the chip include: (A) Adaptive Weighted Image Quality Control Capability, (B) High Speed Operation and (C) External Control Capability for Coding Control. The chip is implemented with CMOS standard cells and contains approximately 38,000 gates.
© (1991) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
H. Uwabu, Eiji Kakii, R. Lacombe, Masanori Maruyama, and Hiroshi Fujiwara "VLSI implementation of a buffer, universal quantizer, and frame-rate-control processor", Proc. SPIE 1605, Visual Communications and Image Processing '91: Visual Communication, (1 November 1991); https://doi.org/10.1117/12.50298
PROCEEDINGS
10 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT


Back to Top