Abstract
Automatic inspection has become an essential part of manufacturing technology for integrated circuit chips. Three trends today in the geometries of integrated circuits and the chips they comprise have serious implications for inspection. The individual devices are getting smaller, with smallest features on some advanced products already crossing the optical resolution threshold; the chip areas are getting larger; and the chips consist of more layers and undergo more processing steps. Not only are the smallest defects harder to see due to the resolution limit, they are much rarer because the tolerable defect density decreases as chip area increases. This paper addresses automated integrated circuit inspection, surveying recent advances, and future challenges. An overview of all inspection operations performed on integrated circuit chips during the manufacturing process is followed by a detailed discussion of pattern defect inspection (PDI) and its unique requirements, such as detection probability, false alarm rate, throughput, and minimum defect size. The core material of the paper consists of a discussion of approaches and systems for PDI, emphasizing recent developments but reviewing older work to set the proper context. Both work reported in the literature and commercial systems are covered.
