1 June 1992 Advanced wafer manufacturing control for yield improvement in the ULSI age
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Abstract
Primarily, this research focuses on a new technical approach to the solution of improving yield in the manufacture of super-flat wafers for ULSI. Secondarily, it introduces current and future concerns relating to the depth of focus issue as well as an overview of the general wafer manufacturing process. Ever-decreasing lithographic linewidths and ever increasing wafer diameter and site size are placing great demands on wafer makers to produce even flatter wafers to achieve the yields necessary for economical device production. Successful next- generation wafer production will rely heavily on proactive quality and manufacturing processes. Indeed, metrology is now being jointly developed to move flatness inspection from a final QC inspection to in-process, quasi-real time, analysis. The theoretical development and implementation of an advanced digital interferometer system into the actual wafer manufacturing process is described. An advanced, workstation-centered, Ethernet LAN interfaced, system is described. The flatness, and change in flatness, with respect to processing and time is accumulated, tracked, and controlled from the beginning of wafer preparation through final mirror polishing. Additionally, the influence of the polishing block (as used in the popular `wax-mount polishing') on overall wafer flatness is investigated. Finally, absolute wafer thickness as an additional process variable is introduced into the analysis.
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Takafumi Yoshida, Takafumi Yoshida, Nobuaki Hayashi, Nobuaki Hayashi, Louis Denes, Louis Denes, Tokuhisa Ito, Tokuhisa Ito, } "Advanced wafer manufacturing control for yield improvement in the ULSI age", Proc. SPIE 1673, Integrated Circuit Metrology, Inspection, and Process Control VI, (1 June 1992); doi: 10.1117/12.59801; https://doi.org/10.1117/12.59801
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