Accurate and precise overlay metrology is essential for the successful fabrication of integrated circuits with submicron critical dimensions. We have continued our investigation into the use of the scanning electron microscope (SEM) for overlay metrology at the device level and for calibration of optics-based systems. Uncoated, multiple level, test structures, fabricated using electron-beam lithography, were measured with the SEM at 0.9 and 20 kV, using off-axis and symmetrical electron detector arrangements. These overlay measurements were then compared to measurements made on the same structures, at 20 kV, after deposition of a thin conducting film. After calibration of the SEM magnification, the average agreement between the uncoated structures and the coated `standard' was better than 5 nm using the symmetrical electron detector. Three (sigma) measurement precision was estimated to be better than 20 nm at 0.9 kV in the absence of charging. Average tool induced shift was approximately -3 nm. The SEM was also used to measure the poly gate to recessed oxide overlay, after etch, of experimental 0.2 - 0.25 micrometers gate width CMOS devices. A comparison to optical measurements, made at the resist level on large marks at the corners of the chips, showed an average difference of 30 - 40 nm in most cases. The experimental results outlined in this paper strongly suggest that the SEM can be used to make accurate overlay measurements of actual devices and may be useful for calibration of optics-based overlay tools.