With device fabrication costs escalating dramatically each year and competition intensifying on a global level, chipmakers are seeking alternative equipment and fab designs to obtain an economic and technical edge. Nowhere is this more apparent than in the lithography area where equipment decisions greatly influence both the cost and performance of the production facility.
This economic incentive has led to extensive use of intermix lithography. With this approach, less costly, more productive systems can be used to pattern the noncritical layers while saving the expensive, advanced performance tools for the critical levels. In the past, the majority of intermixing has occurred between steppers and projection aligners. However, due to increasingly complex device designs, intermix applications have expanded to include 1:1 steppers for noncritical levels, and reduction steppers for critical layers. The economic advantages inherent in this methodology are substantial. Productivity is increased and cost- per-wafer processed reduced for even the most sophisticated ICs.
This paper will describe a lithographic intermix process for a high volume, l|im CMOS process using Ultratech 1:1 and Nikon 5:1 steppers.