28 August 1992 Programmable timing generator for focal plane array testing and operation
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This paper describes a programmable timing generator designed and built to provide timing for focal plane arrays. The timing generator hardware consists of a plug-in board for a PC/XT/AT/386/486 personal computer. The board features 24 output channels, data rates from 175 Hz to 10 MHz, two levels of nested looping, and allows the bit rate to be changed while routine is being executed. Associated software includes a pattern editor, timing routine compiler, memory loader, and generator controller. The board has been successfully used to operate a 4 X 138 X 128 HgCdTe infrared array, a 2098 X 3 linear CCD array, and a 1024 X 1024 full-frame readout CCD. Although intended for use with focal plane arrays, the timing generator can be used in any application where multiple channels of complex and repeated timing are desired. For example, it was used to emulate a TMSC30 digital signal processor serial interface. The timing generator and associated software has proven to be easy to use, and take advantage of the PC/XT/AT/386/486 compatibility and popularity. The board is inexpensive due to the use of standard CMOS logic and one programmable gate array. The programmable part allows the design to be easily upgraded. Future plans include an upgrade to 3 levels of looping.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Thomas H. Ebben, "Programmable timing generator for focal plane array testing and operation", Proc. SPIE 1693, Surveillance Technologies II, (28 August 1992); doi: 10.1117/12.138075; https://doi.org/10.1117/12.138075


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