A new signal processor (SP) architecture has been designed by SPAR to meet the signal processing requirements of tactical infrared search and surveillance (IRSS) systems. The new SP, which can operate in a dual infrared (IR) spectral band configuration, effectively decouples high volume, low latency pixel processing from lower volume, data-dependent detection processing. It enables IRSS SPs to be hosted on heterogeneous multiprocessor networks whose components can be individually matched to the requirements of each process, thus offering flexibility and high growth potential. Pixel processing includes background prefiltering, local feature extraction for adaptive filter selection from multiple filter banks, spatial filtering for threat signal-to-background-noise enhancement, and adaptive thresholding for data detection. Detection processing compares incoming data detections against a target threshold, identifies and reports potential targets, and updates the adaptation parameters that are used to compute detection thresholds in order to maintain constant false alarm rate (CFAR) control. The new nonlinear CFAR process for detection processing utilizes signal processor resources more productively, and can be used to optimize the tracking performance of the detection post-processor. A prototype of the new SP architecture, hosted on the U.S. Navy standard AN/UYS-2 signal processor operating with an AT&T DSP3 processor, has demonstrated improved performance in terms of higher probability of detections (Pd) at a lower detection loading for fixed false alarm rate under clutter and blue sky backgrounds. Improvements in other performance metrics have been proven by software simulation.