1 March 1992 Parallel architecture for a multiple-input fuzzy logic controller
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Abstract
A hardware accelerator that performs fuzzy learning, fuzzy inference, and defuzzification strategy computations is presented. The hardware is based on two-valued logic. A universal space of 25 elements with five levels each is supported. To achieve a high processing rate for real-time applications, the basic units of the accelerator are connected in a four-level pipeline. The accelerator can receive two parallel fuzzy data as inputs. A flag will be set if the fuzzy model R(u,w), constructed in a learning process, exhibits the property as follows: for all (u,w) belonging to the set UXW, R(u,w) equals 1. At a clock rate of 20 MHz, the accelerator can perform more than 1,400,000 fuzzy logic inferences per second on multi- dimensional fuzzy data.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Marian S. Stachowicz, Marian S. Stachowicz, Janos Grantner, Janos Grantner, Larry L. Kinney, Larry L. Kinney, "Parallel architecture for a multiple-input fuzzy logic controller", Proc. SPIE 1707, Applications of Artificial Intelligence X: Knowledge-Based Systems, (1 March 1992); doi: 10.1117/12.56880; https://doi.org/10.1117/12.56880
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