16 September 1992 Analysis of parallel implementations of an artificial neural network on SIMD systems
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Abstract
Implementation of an artificial neural network to solve a character recognition problem on highly parallel, single-instruction-multiple-data (SIMD) machines is described. A SIMD simulator workbench developed to evaluate performance of various 1, 4, 8, and 16-bit processor architectures is used for experimentation. A feed-forward neural network with 25, 25, and 3 nodes at the input, hidden, and output layers is trained by error back-propagation to classify characters represented in a pixel grid in the presence of randomly introduced pixel-flip noise. Each node in the neural network is assigned to a processor, with weights distributed across the array. Outputs of each layer are broadcast to the inputs of the next layer via the array's interprocessor communication network. The available number of processors for the network is limited to an array of size 25 X 25. Experimental results from each of the architectures supported in the simulator workbench are presented and analyzed.
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Todd C. Marek, Todd C. Marek, } "Analysis of parallel implementations of an artificial neural network on SIMD systems", Proc. SPIE 1709, Applications of Artificial Neural Networks III, (16 September 1992); doi: 10.1117/12.140048; https://doi.org/10.1117/12.140048
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