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1 August 1992 Architecture and some properties of digital circuits with boundary scan
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Abstract
The paper presents basic properties of digital circuits, with a boundary scan testing (BST) subsystem in the circuit architecture. The paper describes the operation and states for test access port controller (TAPC) built in the subsystem. A self-test procedure is presented, based on pseudo-random test generation and signature analysis, done by linear feedback shift registers (LFSR), configured with boundary scan register cells. Characteristics of the pseudo- random signal generator were obtained by simulation method.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jerzy Kern "Architecture and some properties of digital circuits with boundary scan", Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); https://doi.org/10.1117/12.131016
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