CUPLAND: behavioral level description compiler for designing of PLD-based circuits

Stanislaw Deniziak; Krzysztof Sapiecha

doi:10.1117/12.131021

1 August 1992 CUPLAND: behavioral level description compiler for designing of PLD-based circuits

Stanislaw Deniziak, Krzysztof Sapiecha

Proceedings Volume 1783, International Conference of Microelectronics: Microelectronics '92; (1992) https://doi.org/10.1117/12.131021
Event: International Conference on Microelectronics, 1992, Warsaw, Poland

Abstract

P-CAD's CUPL is one of the most popular tools for translating a functional description of the circuit into its corresponding PLD-based structure. However, CUPL's input format describes a circuit at the very low level. Moreover, it requires an early selection of target PLD devices that is particularly inconvenient when more complex circuitry is considered. Therefore, designing of large circuits with the help of CUPL is tiring and time consuming. In the paper, another concept is investigated. Behavioral description of the circuit is formulated using procedural CHDL called UPLAND. Then, this description is automatically translated into its corresponding CUPL input format where target PLD devices are optional. The paper introduces UPLAND and outlines the principles of CUPLAND compiler work. An example is given which illustrates CUPLAND efficiency.

Citation Download Citation

Stanislaw Deniziak and Krzysztof Sapiecha "CUPLAND: behavioral level description compiler for designing of PLD-based circuits", Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); https://doi.org/10.1117/12.131021

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