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9 February 1993 1.0625-Gbit/s fiber channel transmitter/receiver chipset implemented in ECL with on-chip phase-locked loop
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Abstract
A mixed signal Application-Specific Standard Product (ASSP) which integrates custom phase-locked loop (PLL) based clock recovery and clock synthesis functions with configurable logic cells provides a two-chip solution for 266 to 1062 Mbit/s Fiber Channel applications. The chipset performs parallel-to-serial and serial-to-parallel conversion, 8B/10B encoding/decoding functions, framing, and primitive signal/sequence generation and identification. The on-chip clock synthesis PLL generates the high-speed serial clock from a low-speed reference. The on-chip clock recovery PLL is capable of synchronizing directly to incoming digital signals, while simultaneously retiming and regenerating the data stream. The chips are designed using an advanced one-micron bipolar process with `Turbo' cells resulting in substantially reduced static power and output skews. Models for the PLL functions have been developed for use in logic simulation platforms. These models allow full chip-level and system-level simulation capabilities.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Thomas G. Palkert, Frederick Taverdians, Sharon Weintraub, Bruce H. Coy, Ali Wehbi, and Marc D. Friedmann "1.0625-Gbit/s fiber channel transmitter/receiver chipset implemented in ECL with on-chip phase-locked loop", Proc. SPIE 1784, High-Speed Fiber Networks and Channels II, (9 February 1993); https://doi.org/10.1117/12.141091
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