Breakdown voltage of submicron MOSFETs in fully depleted SOI

Neal Kistler; Eric Ver Ploeg; Jason C.S. Woo; James D. Plummer

doi:10.1117/12.139352

14 January 1993 Breakdown voltage of submicron MOSFETs in fully depleted SOI

Neal Kistler, Eric Ver Ploeg, Jason C.S. Woo, James D. Plummer

Proceedings Volume 1802, Microelectronics Manufacturing and Reliability; (1993) https://doi.org/10.1117/12.139352
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States

Abstract

The fully depleted silicon-on-insulator (SOI) MOSFET is a candidate for deep-submicron VLSI due to the numerous advantages over bulk silicon devices, including resistance to short- channel effects, reduced parasitic capacitances, improved subthreshold slope, and higher transconductance. However, these devices can exhibit a low source-drain breakdown voltage, which is a result of the triggering of the parasitic bipolar transistor. The breakdown voltage in fully depleted SOI MOSFET's has been studied as a function of both silicon film thickness and channel length. In the long-channel regime (> 2 micrometers ), the breakdown voltage is found to decrease as film thickness is decreased. This is attributed to increasing lateral electric fields as film thickness decreases. As channel lengths are reduced, however, the ultra-thin devices eventually exhibit higher breakdown voltages than the thicker devices. The higher breakdown voltage in the ultra-thin devices is attributed to improved resistance to punchthrough and charging effects. As the channel length is reduced, there is a transition from a bipolar-dominated breakdown regime to a punchthrough-dominated regime. The channel length at which punchthrough becomes significant is greater in thicker films, resulting in lower breakdown voltages at deep-submicron channel lengths. Therefore, ultra-thin films may be preferred over thicker SOI for deep-submicron VLSI.

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Neal Kistler, Eric Ver Ploeg, Jason C.S. Woo, and James D. Plummer "Breakdown voltage of submicron MOSFETs in fully depleted SOI", Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993); https://doi.org/10.1117/12.139352

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KEYWORDS

Field effect transistors

Resistance

Transistors

Silicon

Very large scale integration

Ionization

Manufacturing

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