Translator Disclaimer
14 January 1993 Investigation into bake-reversible low-level ESD-induced leakage
Author Affiliations +
Proceedings Volume 1802, Microelectronics Manufacturing and Reliability; (1993)
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States
Electro-State Discharge (ESD) induced leakage in output transistors is a serious concern in modern CMOS processes. Previous papers have attributed an increase in output leakage after Human Body Model (HBM) ESD testing, to the formation of small silicon melt filaments in the drain of output N-channel transistors. These filaments are apparently caused by current localization and thermal runaway at the drain of the output transistor when driven too far into parasitic bipolar breakdown by an ESD pulse. In this paper, an in depth analysis of the melt filament related leakage characteristics, as well as physical failure analysis utilizing the techniques of Specific Area Cross-section Transmission Electron Microscopy (SAXTEM) was performed. With HBM stressing in the range 500 V to 6000 V, the induced leakage rarely exceeded the maximum specified device leakage current, but was observed to vary widely at a given stress voltage. With this wide leakage distribution it was shown that the measured threshold failure voltage depended on both the failure criteria for leakage during testing, and the sample size tested. This could significantly impact reliability testing and prediction. In addition, the stressed devices were observed to undergo a temperature dependent partial leakage recovery with time. Physical failure analysis was performed on leaking outputs in order to gain more insight into the actual mechanism responsible for the leakage. A Focused Ion Beam tool (FIB) was used to prepare thin cross sections containing the localized damaged regions. TEM analysis revealed silicon melt filaments, less than 100 angstroms thick, at the Si-SiO2 interface above the LDD portion of the drain. Larger regions of heat damaged silicon were evident at both ends of these filaments. This may be the first application of TEM analysis to investigate ESD induced melt filaments in silicon. By using this technique as opposed to more conventional approaches it was possible to clearly image the damaged regions and gain greater insight into the nature of the mechanisms responsible.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Nicholas Dickson, James W. Miller, Mark Jackson, Stella Kohn, Ronald E. Pyle, and Sudhindra Tatti "Investigation into bake-reversible low-level ESD-induced leakage", Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993);

Back to Top