Paper
14 January 1993 Strategy for continuous improvement in IC manufacturability, yield, and reliability
Dean J. Dreier, Mark Berry, Phil Schani, Michael Phillips, Joe Steinberg, Gary DePinto
Author Affiliations +
Proceedings Volume 1802, Microelectronics Manufacturing and Reliability; (1993) https://doi.org/10.1117/12.139359
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States
Abstract
Continual improvements in yield, reliability and manufacturability measure a fab and ultimately result in Total Customer Satisfaction. A new organizational and technical methodology for continuous defect reduction has been established in a formal feedback loop, which relies on yield and reliability, failed bit map analysis, analytical tools, inline monitoring, cross functional teams and a defect engineering group. The strategy requires the fastest detection, identification and implementation of possible corrective actions. Feedback cycle time is minimized at all points to improve yield and reliability and reduce costs, essential for competitiveness in the memory business. Payoff was a 9.4X reduction in defectivity and a 6.2X improvement in reliability of 256 K fast SRAMs over 20 months.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dean J. Dreier, Mark Berry, Phil Schani, Michael Phillips, Joe Steinberg, and Gary DePinto "Strategy for continuous improvement in IC manufacturability, yield, and reliability", Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993); https://doi.org/10.1117/12.139359
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Cited by 2 scholarly publications.
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KEYWORDS
Reliability

Manufacturing

Failure analysis

Semiconducting wafers

Inspection

Yield improvement

Holography

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