14 January 1993 Wafer level reliability
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Proceedings Volume 1802, Microelectronics Manufacturing and Reliability; (1993) https://doi.org/10.1117/12.139345
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States
Abstract
This paper presents a perspective on the use of Wafer Level Reliability (WLR) in developing a competitive quality/reliability program. WLR is defined as accelerated stressing of test structures at the wafer level. The pros and cons of WLR are considered in five application areas: process control; qualification; benchmarking; reliability monitoring/prediction; and modeling. WLR examples are discussed in the areas of oxide breakdown, hot carrier degradation, and electromigration. The need to develop physical, statistical, and geometrical models to extrapolate from WLR results to actual products is discussed.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Theodore A. Dellin, William M. Miller, Donald G. Pierce, Eric S. Snyder, "Wafer level reliability", Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993); doi: 10.1117/12.139345; https://doi.org/10.1117/12.139345
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