Translator Disclaimer
14 January 1993 Wafer level reliability
Author Affiliations +
Proceedings Volume 1802, Microelectronics Manufacturing and Reliability; (1993)
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States
This paper presents a perspective on the use of Wafer Level Reliability (WLR) in developing a competitive quality/reliability program. WLR is defined as accelerated stressing of test structures at the wafer level. The pros and cons of WLR are considered in five application areas: process control; qualification; benchmarking; reliability monitoring/prediction; and modeling. WLR examples are discussed in the areas of oxide breakdown, hot carrier degradation, and electromigration. The need to develop physical, statistical, and geometrical models to extrapolate from WLR results to actual products is discussed.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Theodore A. Dellin, William M. Miller, Donald G. Pierce, and Eric S. Snyder "Wafer level reliability", Proc. SPIE 1802, Microelectronics Manufacturing and Reliability, (14 January 1993);


Emcore VCSEL failure mechanism and resolution
Proceedings of SPIE (February 05 2010)
Yield issues with local interconnect
Proceedings of SPIE (August 28 1998)
Bad vias are the cause for electrical test yield losses...
Proceedings of SPIE (August 28 1998)
Statistical reliability control from an IC user's perspective
Proceedings of SPIE (September 15 1993)

Back to Top