Microtrenching during polysilicon plasma etch

Steve W. Swan; Daniel A. Corliss

doi:10.1117/12.142906

16 April 1993 Microtrenching during polysilicon plasma etch

Steve W. Swan, Daniel A. Corliss

Proceedings Volume 1803, Advanced Techniques for Integrated Circuit Processing II; (1993) https://doi.org/10.1117/12.142906
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States

Abstract

Micro-trenching occurs during plasma polysilicon etch for features with sub 0.5 micrometers spaces and thin gate dielectric. The trenches, which form near the base of etched features as a series of holes through the gate dielectric and into the underlying silicon, are the result of ion scattering off the resist/polysilicon sidewall. By studying structures with varying feature spacing and resist thicknesses we were able to determine that the depth and location of the trenches are related to the aspect ratio (height:width) of the structure, the sidewall profile of the resist/polysilicon line, and the process conditions during over-etch. Ion scattering which causes the micro-trenching is enhanced under conditions of increasing aspect ratio and decreasing sidewall angle of the etched feature.

Citation Download Citation

Steve W. Swan and Daniel A. Corliss "Microtrenching during polysilicon plasma etch", Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); https://doi.org/10.1117/12.142906

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