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16 April 1993 Sloped etching of highly phosphorous doped polysilicon developed with response surface methodology
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Proceedings Volume 1803, Advanced Techniques for Integrated Circuit Processing II; (1993) https://doi.org/10.1117/12.142914
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States
Abstract
Plasma etching of highly phosphorous doped polysilicon gate structures can yield undercutting of the poly lines creating a negative slope of the vertical edge of the polysilicon or a notching at the bottom of the lines. In order to achieve good step coverage of subsequent deposited oxides and to facilitate the removal of stringers during etching of a poly II layer in EEPROM structures, such a profile cannot be acceptable. This paper describes the development of a chlorine-based reactive ion etching (RIE) process that exhibits slightly positively sloped (85 degree(s) angle) profiles of the first polysilicon layer. Response surface methodology was used to identify most important process parameters and to characterize the final process. The results obtained at the different stages are presented in detail.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Joerg Jasper "Sloped etching of highly phosphorous doped polysilicon developed with response surface methodology", Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); https://doi.org/10.1117/12.142914
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