1 November 1992 VLSI Reed-Solomon decoder
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Proceedings Volume 1818, Visual Communications and Image Processing '92; (1992) https://doi.org/10.1117/12.131377
Event: Applications in Optical Science and Engineering, 1992, Boston, MA, United States
Abstract
In this paper, a VLSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provides both erasure and error correcting capability. In order to reduce the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed. And the overall architecture features parallel and pipelined structure, making a real time decoding possible. It is shown that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the architecture based on the recursive Euclid algorithm.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yong Hwan Kim, Young Mo Chung, Sang Uk Lee, "VLSI Reed-Solomon decoder", Proc. SPIE 1818, Visual Communications and Image Processing '92, (1 November 1992); doi: 10.1117/12.131377; https://doi.org/10.1117/12.131377
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