In this paper, a VLSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provides both erasure and error correcting capability. In order to reduce the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a recursive structure so that the number of cells for computing the errata locator polynomial can be reduced. Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementation, provided an improvement in the decoding speed. And the overall architecture features parallel and pipelined structure, making a real time decoding possible. It is shown that the proposed VLSI architecture is more efficient in terms of VLSI implementation than the architecture based on the recursive Euclid algorithm.