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1 November 1992 Hardware system for computing image velocity in real time
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Proceedings Volume 1823, Machine Vision Applications, Architectures, and Systems Integration; (1992)
Event: Applications in Optical Science and Engineering, 1992, Boston, MA, United States
A multi-purpose hardware system for processing images at video rates is described. Image sequence hardware for temporal analysis in realtime (ISHTAR) uses 18 TI TMS320c40 (c40) DSPs to process input from a CCD camera or VCR source. The hardware architecture consists of a pipeline of nine processor boards, each with two c40 processors, the whole system being synchronized by the vertical sync of the input device. This enables the calculation of a number of two dimensional convolutions to be achieved at video frame rates with a delay between the input and the output dictated by the length of the pipeline. The system is fully reconfigurable in software and partially reconfigurable in hardware so that many different types of image processing algorithms can be implemented. The specific application of a generalized gradient model to measure image motion is described, outlining the particular program structure dictated by the hardware design. The SUN 4 host has access to each processor and has the ability to change parameters and program control while the system is running. In this way active control feedback loops can be employed, particularly when the motion of the camera is under the host control, forming an active vision system. Simulations using real image sequences are presented.
© (1992) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter J. Sobey, Shigeru Sasaki, Martin G. Nagle, Takashi Toriu, and Mandyam V. Srinivasan "Hardware system for computing image velocity in real time", Proc. SPIE 1823, Machine Vision Applications, Architectures, and Systems Integration, (1 November 1992);


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