GaAs heteroepitaxy with submicron Si CMOS: an experimental compatibility study

Lawrence Anthony Hornak; Stuart K. Tewksbury; Homi E. Nariman

doi:10.1117/12.147077

1 July 1993 GaAs heteroepitaxy with submicron Si CMOS: an experimental compatibility study

Lawrence Anthony Hornak, Stuart K. Tewksbury, Homi E. Nariman

Proceedings Volume 1849, Optoelectronic Interconnects; (1993) https://doi.org/10.1117/12.147077
Event: OE/LASE'93: Optics, Electro-Optics, and Laser Applications in Scienceand Engineering, 1993, Los Angeles, CA, United States

Abstract

Routine use of optical interconnections in MCM based computing systems ideally favors monolithic integration to achieve both high density and manufacturability. The central issue facing this monolithic evolutionary path is the compatibility of both III-V semiconductor growth and subsequent optoelectronic device and passive optical interconnection processing with existing and future generations of CMOS and advanced packaging technology. The influence of GaAs heteroepitaxy and device processing on submicron CMOS is the subject of an ongoing program seeking to experimentally determine compatibility conflicts and through understanding of their physical mechanisms identify directions for achieving GaAs heteroepitaxy compatibility with future CMOS generations. Following a brief review of GaAs heteroepitaxy compatibility concerns, preliminary results from the current experimental program exploring the influence of both thermally simulated and actual GaAs heteroepitaxy on commercial 0.9 micrometers (0.6 micrometers minimum channel length) CMOS are presented including parametric device modeling, interface state, and hot electron measurements of experimental test lot devices.

Citation Download Citation

Lawrence Anthony Hornak, Stuart K. Tewksbury, and Homi E. Nariman "GaAs heteroepitaxy with submicron Si CMOS: an experimental compatibility study", Proc. SPIE 1849, Optoelectronic Interconnects, (1 July 1993); https://doi.org/10.1117/12.147077

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