12 July 1993 Large-pitch multiple-output 128x256-element area array
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A high speed imager capable of 1 gigacycle frame rate was developed with 80 micrometers X 80 micrometers pixels. A special multi-phase readout shift register and parallel to serial transfer structure are designed for high charge transfer efficiency operation across a large 80 micrometers pitch at high speed. A total of 64 outputs each designed to operate at 16 MHz are distributed around the array. In order to minimize power dissipation, a single output MOSFET operating in conjunction with an off-chip transimpedance amplifier was used. A photodiode, interline transfer pixel architecture was used with lateral antiblooming and exposure control capability.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
William D. Washkurak, Savvas G. Chamberlain, "Large-pitch multiple-output 128x256-element area array", Proc. SPIE 1900, Charge-Coupled Devices and Solid State Optical Sensors III, (12 July 1993); doi: 10.1117/12.148598; https://doi.org/10.1117/12.148598

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