20 May 1993 Design and implementation of a pixel image scanner
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In this paper the design of a pixel image scanner (PIS) and its interface with two processors, the image processor (backend) and main processor is proposed. The detailed hardware logic needed for the main processor to address the 256 X 256 pixel image sensors locations, and the 64 K X 8 bit FIFO memory for buffering the digital data acquired for the PIS and which is to be made available to the backend (image) processor is presented. A two port static RAM, interfaces the two processors. The dual port RAM design is capable of generating an interrupt to the main processor in order to inform the availability of processed data. All the timing, control signals address, and data lines needed for the main processor are also discussed.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Nikolaos G. Bourbakis, Nikolaos G. Bourbakis, W. Tariq, W. Tariq, N. Pereira, N. Pereira, } "Design and implementation of a pixel image scanner", Proc. SPIE 1901, Cameras, Scanners, and Image Acquisition Systems, (20 May 1993); doi: 10.1117/12.144787; https://doi.org/10.1117/12.144787


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