4 August 1993 Absolute pattern placement metrology on wafers
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Absolute pattern placement metrology on wafers yield significant improvements for tool design and tool engineering. Error limits needed for advanced lithography processes are presented, error sources involved in wafer metrology for characterizing steppers are shown. The algorithm used to extract the characteristic image of the reticle is outlined. Static repeatability of 3.3 nm for and of 8 nm for die grid was obtained (maximum, 3-standard deviations). Nominal accuracy was 7 nm (lens map) and 32 nm (die grid) as obtained by comparing measurements with wafer orientations of 0, 90, 180 and 270 degrees.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Uwe Mickan, Uwe Mickan, Klaus Rinn, Klaus Rinn, } "Absolute pattern placement metrology on wafers", Proc. SPIE 1926, Integrated Circuit Metrology, Inspection, and Process Control VII, (4 August 1993); doi: 10.1117/12.148998; https://doi.org/10.1117/12.148998


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