25 October 1993 64 x 64 thresholding photodetector array for optical pattern recognition
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A high performance 32 X 32 peak detector array is introduced. This detector consists of a 32 X 32 array of thresholding photo-transistor cells, manufactured with a standard MOSIS digital 2-micron CMOS process. A built-in thresholding function that is able to perform 1024 thresholding operations in parallel strongly distinguishes this chip from available CCD detectors. This high speed detector offers responses from one to 10 milliseconds that is much higher than the commercially available CCD detectors operating at a TV frame rate. The parallel multiple peaks thresholding detection capability makes it particularly suitable for optical correlator and optoelectronically implemented neural networks. The principle of operation, circuit design and the performance characteristics are described. Experimental demonstration of correlation peak detection is also provided. Recently, we have also designed and built an advanced version of a 64 X 64 thresholding photodetector array chip. Experimental investigation of using this chip for pattern recognition is ongoing.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Harry Langenbacher, Harry Langenbacher, Tien-Hsin Chao, Tien-Hsin Chao, Timothy Shaw, Timothy Shaw, Jeffrey W. Yu, Jeffrey W. Yu, "64 x 64 thresholding photodetector array for optical pattern recognition", Proc. SPIE 1959, Optical Pattern Recognition IV, (25 October 1993); doi: 10.1117/12.160305; https://doi.org/10.1117/12.160305


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