4 November 1993 Novel memory architecture for video signal processor
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Proceedings Volume 1976, High-Definition Video; (1993) https://doi.org/10.1117/12.161478
Event: Video Communications and Fiber Optic Networks, 1993, Berlin, Germany
An on-chip memory architecture for video signal processor (VSP) is proposed. This memory structure is a two-level design for the different data locality in video applications. The upper level--Memory A provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level--Memory B provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. The needed memory size is decided by the memory usage analysis for video algorithms and the number of function units. Both levels of memory adopted a dual-port memory scheme to sustain the simultaneous read and write operations. Especially, Memory B uses multiple one-read-one-write memory banks to emulate the real multiport memory. Therefore, one can change the configuration of Memory B to several sets of memories with variable read/write ports by adjusting the bus switches. Then the numbers of read ports and write ports in proposed memory can meet requirement of data flow patterns in different video coding algorithms. We have finished the design of a prototype memory design using 1.2- micrometers SPDM SRAM technology and will fabricated it through TSMC, in Taiwan.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jen-Sheng Hung, Jen-Sheng Hung, Chia-Hsing Lin, Chia-Hsing Lin, Chein-Wei Jen, Chein-Wei Jen, "Novel memory architecture for video signal processor", Proc. SPIE 1976, High-Definition Video, (4 November 1993); doi: 10.1117/12.161478; https://doi.org/10.1117/12.161478

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