1 November 1993 Highly pipelined VLSI architecture for computation of fast Fourier transforms
Author Affiliations +
Abstract
An on-chip VLSI architecture for computation of Fourier transforms is presented. It performs the arithmetic operations in a digit-level pipeline fashion. For this purpose, the implementation of arithmetic operators is based on on-line (i.e., digit-serial and most significant digit first) arithmetic, and the transforms are performed by a parallel-pipeline version of the Cooley- Tukey fast Fourier transform (FFT) algorithm.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hong-Jin Yeh, Hong-Jin Yeh, } "Highly pipelined VLSI architecture for computation of fast Fourier transforms", Proc. SPIE 2027, Advanced Signal Processing Algorithms, Architectures, and Implementations IV, (1 November 1993); doi: 10.1117/12.160427; https://doi.org/10.1117/12.160427
PROCEEDINGS
10 PAGES


SHARE
RELATED CONTENT


Back to Top