23 June 1993 Prototype coprocessor for image algebra operations
Author Affiliations +
The logical architecture for this effort was developed at Wright Laboratory. Oak Ridge National Laboratory has taken the design and reordered the data flow to allow a physical architecture to be prototypes using DSP chips, transputers, or VLSI. The design allows image algebra operations to be executed in a staged pipeline at nearly the same throughput as a memory to memory transfer. The control is by direct memory access from the host, in this case a SUN SPARC II. Reduce operations such as sum, maximum, and minimum are captured as by-products of the pipeline operation.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Patrick C. Coffield, Patrick C. Coffield, Matthew B. Scudiere, Matthew B. Scudiere, } "Prototype coprocessor for image algebra operations", Proc. SPIE 2030, Image Algebra and Morphological Image Processing IV, (23 June 1993); doi: 10.1117/12.146670; https://doi.org/10.1117/12.146670

Back to Top