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15 September 1993 Effects of ILD thickness and slope-etch depth on via performance and metal filling characteristics
Gregory W. Grynkewich; John L. Freeman; Wayne K. Morrow; Ping Wang; Robert Woodburn
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Proceedings Volume 2090, Multilevel Interconnection: Issues That Impact Competitiveness; (1993) https://doi.org/10.1117/12.156532
Event: Microelectronic Processing '93, 1993, Monterey, CA, United States
Abstract
The interaction of ILD (interlevel dielectric) thickness with slope etch depth on the performance of single and stacked vias has been characterized on a four-layer metal high performance bipolar device. Both wet and dry slope etches, which have significantly different cross sectional profiles, were investigated. As expected, the aspect ratio (AR) of the vertical wall of the via was critical in determining how well the via filled with hot Al/Cu: at AR > 0.8, some open vias were observed. However, it was also found that excessive dry slope etch could cause via performance to degrade. For a given ILD thickness, increasing the depth of the dry slope etch could cause via resistance to increase. In addition, for a constant RIE time (varied ILD thickness), deeper slope etches resulted in higher via resistance. These results are discussed in terms of an interaction between the dry slope etch and the amount of RIE overetch time.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
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Gregory W. Grynkewich, John L. Freeman, Wayne K. Morrow, Ping Wang, and Robert Woodburn "Effects of ILD thickness and slope-etch depth on via performance and metal filling characteristics", Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); https://doi.org/10.1117/12.156532
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