In this work an inter-metal dielectric (IMD) planarization process, developed for multimetal submicron technology devices, is presented. The feasibility to build up to five metal levels with W blanket-etch back stacked plug interconnections is shown, using a new Spin On Glass (SOG) material and a semi-integrated planarization process in which a bake, a SOG Partial Etch Back (PEB), and a TEOS oxide cap layer deposition are done sequentially in the same cluster tool. The presented planarization process allows a very low over-etch for the W etch back step at each plug level and, consequently, a quite good control of the plug recession as required by stacked vias. This new process has effectively extended the life of an existing SOG Partial Etch Back process already established on existing equipment. Planarization process performances have been tested on an advanced triple metal device with stacked W plugs and on a test device with five metal levels with various metal pitches. Process results are presented in terms of defect density, repeatability, and electrical tests on stacked via chain structures.