15 September 1993 Wafer level reliability: competitiveness and implementation issues
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How does wafer level reliability assessment and testing methodology integrate into the semiconductor manufacturer's overall reliability assurance and improvement strategy? What wafer level tests are appropriate and when should they be utilized? Wafer level reliability has made the evolutionary step from academia to manufacturing actuality. This paper provides a conceptual focus for where and when wafer level reliability is utilized in a state-of-the-art semiconductor manufacturing environment. Special emphasis is placed on the use of wafer level reliability testing for introducing and qualifying new semiconductor technology, as well as controlling production once the technology has been qualified.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jeff S. May, Jeff S. May, Hoang Huy Hoang, Hoang Huy Hoang, } "Wafer level reliability: competitiveness and implementation issues", Proc. SPIE 2090, Multilevel Interconnection: Issues That Impact Competitiveness, (15 September 1993); doi: 10.1117/12.156521; https://doi.org/10.1117/12.156521


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