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15 February 1994 Sub-0.5-μm polysilicon etching on a MERIE system: a case study in manufacturing
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A polysilicon etch process designed for use in manufacturing must yield stable results for critical dimensions, line profile, gate oxide loss, gate oxide damage, defect density, and throughput; all of which must meet the desired specifications for the device being fabricated. A process that meets these requirements has been developed for undoped polysilicon with nominal linewidth of 0.45 micrometers and gate dielectric thickness of 90 angstroms on a single wafer (150 mm) magnetically enhanced reactive ion etch (MERIE) system. The impact of plasma induced charging on device performance is discussed using test results of time dependent dielectric breakdown for structures with polysilicon: gate antenna ratios in the range of 1:1 to 10,000.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Steve W. Swan and Graham W. Hills "Sub-0.5-μm polysilicon etching on a MERIE system: a case study in manufacturing", Proc. SPIE 2091, Microelectronic Processes, Sensors, and Controls, (15 February 1994);

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