Effect of layout variations on noise figure in a digital GaAs MESFET technology

Charles Chang; C. Y. Kwok; Peter M. Asbeck

doi:10.1117/12.175255

2 May 1994 Effect of layout variations on noise figure in a digital GaAs MESFET technology

Charles Chang; C. Y. Kwok; Peter M. Asbeck

Author Affiliations +

Proceedings Volume 2149, Technologies for Optical Fiber Communications; (1994) https://doi.org/10.1117/12.175255
Event: OE/LASE '94, 1994, Los Angeles, CA, United States

Abstract

Digital GaAs FET technology, with its high level of integration, can be employed in high-speed optical systems for optical detector amplifiers as well as for baseband processing. However, the WSi gate of the digital GaAs FETs results in high gate resistance, which increases the noise figure as compared to the Ti/Pt/Au `T' shaped gates used in microwave FETs. In high-speed optical receiver applications, the noise in the FET based amplifier dominates the entire system noise. In this work, we use the 1st and 2nd layer metal to reduce the gate resistance in order to improve the minimum noise figure through layout variations compatible with production digital technology.

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Charles Chang, Charles Chang, C. Y. Kwok, C. Y. Kwok, Peter M. Asbeck, Peter M. Asbeck, } "Effect of layout variations on noise figure in a digital GaAs MESFET technology", Proc. SPIE 2149, Technologies for Optical Fiber Communications, (2 May 1994); doi: 10.1117/12.175255; https://doi.org/10.1117/12.175255

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