The OETC is an industry consortium of Martin Marietta, AT&T, Honeywell, and IBM, supported by ARPA, to develop key optoelectronic components that advance interconnect technology beyond current cost, speed, and density barriers. OETC's structure includes a users application group and a research associates group for continuous technology exchange and user feedback, combining both military and commercial perspectives, goals, and strategies. The OETC is developing a testbed that integrates all board-to-board data paths of a high performance processor with optical data links. The paper describes progress on the program including technical developments, the results of meetings with the users group, and issues remaining to be solved on future programs.

A barrier that has faced insertion of optical interconnections within MCM environments is the absence of generic system-level building blocks suitable for inclusion by system designers within prototype MCM architectures. To obtain system-level acceptance, a stable digital interface with built-in self test, fault tolerance, and relaxation of optomechanical alignment must be provided. To accommodate the rapid technology development implied by chip level requirements, these generic components must provide this system-level stability while also acting as a technology platform from which new generations of optical components and integrated packaging can be evaluated. This paper describes design considerations for a prototype intelligent optical interconnection module (IOIM) to serve as this generic system- level building block. The utility of the IOIM organization is motivated through exploration of the requirements of an optoelectronic interface for a cryo-electronic communication switch prototype.

Cost, reliability, and safety issues for the electronics of mobile platforms force a re- examination of the architectures of platform electronics, particularly for those platforms that will carry people or operate near people. Previous architectures provided a system to control each function, and reliability and safety requirements were met by duplicating components or entire systems. Integration of the activities of the system was accomplished by the operator. As the complexity of the functions increased the workload on the operator became unmanageable and the cost of the electronics became prohibitive. Within the category of mobile platforms, the trend developed in its most extreme form for tactical aircraft avionics. This paper describes the requirements for a data network for a distributed avionic architecture for a tactical aircraft. In many respects, the requirements on a tactical aircraft are more extreme than will be seen in most other mobile platforms; however, the overall distributed architecture, and the data network which allows it to function, is applicable and can be scaled to meet the need.

Free space optical interconnect has provided a promising solution to the effective signal links of the increasing density and complexity in very-large-scale/large-scale integrated circuits. It is getting less affordable if such a system fails just for one tiny physical defect. Our analysis on the potential optical-electrical link failure provides guidelines for future testing and reliable system design. The study of fault models starts by exploring the underlying physical malfunctioning of the opto-electrical components, and their impacts on the assembled systems. We map the physical defects of opto-electronic devices into their corresponding logic-level representation for higher level design consideration. This mapping is chosen for its compatibility and practicability with digital electronic system designs where automated design tools can expedite the design optimization and verification process.

A 32-bit digital optical computer (DOC II) has been implemented in hardware utilizing 8,192 free-space optical interconnects. The architecture exploits parallel interconnect technology by implementing microcode at the primitive level. A burst mode of 0.8192 X 10¹² binary operations per sec has been reliably demonstrated. The prototype has been successful in demonstrating general purpose computation. In addition to emulating the RISC instruction set within the UNIX operating environment, relational database text search operations have been implemented on DOC II.

For the past few years we have been working on the development of an optically interconnected multichip module (MCM). The MCM is composed of a planar transparent substrate, containing thin film electrical connections. GaAs laser array chips and silicon CMOS VLSI chips with integrated photodetectors are flip-chip bonded to one side of the substrate, while computer generated holograms (CGHs) are fabricated on the other side of the substrate. The purpose of this work is to develop the technology to enable high speed and high density connections between chips, MCMs, and PC boards. We believe that the basic approach we use, based on flip-chip and CGH technology, will provide 1-2 orders of magnitude increase in connection performance when compared with conventional electrical connectors.

Recent research indicates that while maintaining a basic mesh-type node layout, which has many proven practical advantages, an increase (from degree-4) in node connectivity can lead to various new and interesting networking properties. In this paper, we discuss possible optical methods to implement such a class of connectivity-enhanced mesh-based interconnect networks. Multiplexing capability that only free-space optics could efficiently offer is utilized in these methods. As particular examples, two interconnect schemes, one for a nonblocking broadcast switching, are described. While the first model, which aims to reduce he overall network diameter using extended node connectivity, offers a compact and scalable geometry and a fast routing capability, the second model, which aims to lower the switching complexity bound for nonblocking multicast interconnect applications, is extendable to multidimensional multiplexing. Advantages of using the free-space optics for implementing the two models are discussed. Some proof-of-principle experimental results are presented.

A free-space optical bus system at the backplane level capable of high-speed data transmission is introduced. The system uses substrate mode holograms to implement broadcasting operations, and each board on the backplane uses the same free-space bus channels for transmitting and receiving signals. The effects of beam displacement on optical crosstalk and bus channel density are discussed. The broadcasting operations for 622 Mb/s signals were experimentally demonstrated.

In this paper, we present a miniaturized compact 3-D optical fan-out interconnect suitable for wafer scale VLSI multichip module optical clock signal distribution. The demonstrated device employs a thin light-guiding substrate in conjunction with a 2-D optical hologram array. The parallel feature among fan-out beams and the planar compact structure convert the unsolvable three spatial and three angular multiple alignment problem into a single-step 2-D planar one, which greatly enhances the packaging reliability. A new design scheme for minimizing throughput power non-uniformity is presented for the first time. A 25 GHz 1-to-42 highly parallel fan-out interconnect was demonstrated with a signal to noise ratio of 10 dB.

A high speed clock distribution network using free space optical interconnects with substrate mode holograms and high speed transmitter/receiver modules is described. An electrically compatible system with signal jitter less than 70/50 ps at 622/840 MHz is demonstrated. To improve the power consumption of receivers, a low noise receiver applying a resonant front end circuit is designed. The receiver performance is presented and the corresponding system issues are discussed.

The paper presents an approximate analysis of the conical diffraction by planar volume gratings. Explicit expressions are derived for the coupling constants and the dephasing between different diffraction orders. The results of the approximate coupled-wave theory are compared with the rigorous numerical solution of the three-dimensional boundary value problem for a specific configuration. A two-wave coupled-wave theory is presented and an analytical solution is given.

Wafer optical interconnections have been fabricated using direct laser writing. Relatively high losses were observed in the channel waveguides. In this work we report the successful reduction of the losses by using a filtered version of the polyimide material. We also describe our on-going work applying this technology for (1) performance evaluation of a 50 to 100 GHz passive repetition-rate doubler and (2) integration of waveguide components with HBTs for systems such as phased array radars.

SHARP is a Navy wide logistics technology development effort aimed at reducing the acquisition costs, support costs, and risks of military electronic weapon systems while increasing the performance capability, reliability, maintainability, and readiness of these systems. Lower life cycle costs for electronic hardware are achieved through technology transition, standardization, and reliability enhancement to improve system affordability and availability as well as enhancing fleet modernization. Advanced technology is transferred into the fleet through hardware specifications for weapon system building blocks of standard electronic modules, standard power systems, and standard electronic systems. The product lines are all defined with respect to their size, weight, I/O, environmental performance, and operational performance. This method of defining the standard is very conducive to inserting new technologies into systems using the standard hardware. This is the approach taken thus far in inserting photonic technologies into SHARP hardware. All of the efforts have been related to module packaging; i.e. interconnects, component packaging, and module developments. Fiber optic interconnects are discussed in this paper.

Variation of the ultrasonic frequency of an acousto-optical modulator produces a tunable grating. For a fixed deflection angle the wavelength of the diffracted light changes. A tuning of operation mode related to the geometrical dimensions is necessary.

The impact of process variation associated with lateral and axial misalignment of flip-chip solder joint based assembly for OE-MCM packaging is analyzed through quasi-static force balance in the system. The effect of variation in solder deposition height, vertical loading, and surface tension coefficient on the alignment, and therefore on the optical performance of the system, is studied.

The rapid increases in IC chip performance have made increasing demands on electronic packaging technology in order to achieve the improvements in system performance that the IC speeds promise. An exciting approach to reducing the signal latency in electronic systems is to go to 3-D packaging, in which closely stacked boards are coupled with large numbers of vertical interconnects distributed over the area of the boards. In part because of a perception that electrical Z interconnect approaches such as `fuzz buttons' would seriously compromise signal performance due to parasitic lumped inductance effects, optical inter-board interconnect approaches have been proposed for this application. This paper examines the capabilities of normal metal electronic interconnects in meeting the requirements for 2-D and 3-D MCM applications, and to elucidate the areas in which more exotic approaches such as superconducting or optical interconnects offer significant potential advantages. It is pointed out that for short interconnects, such as those inside of a 2-D or 3-D MCM, normal metal interconnects can be designed to give excellent performance for digital signal frequencies up to at least 5 GHz.

The inversion channel technology is a new approach to monolithic optoelectronic integration that offers the possibility of FET logic, optical detection, and laser emission from a single chip. The detection is performed by the three terminal configuration of the DOES biased in the off state. Incident light switches the DOES into the on state and recovery from the on state is provided by the conduction of electrons from the inversion channel through a FET connected to the third terminal. In this paper we demonstrate the functionality of this operation with an OEIC that integrates the three terminal DOES device with four FETs. The operation is discussed both as an optical clock and as an electrically clocked optical gate. Sensitivity issues are considered.

Semiconductor lasers with dry etched facets are of interest for monolithic 2-D coherent applications such as optical interconnects and optoelectronic integrated circuits. This paper reports recent development on this area including high-performance 3 X 3 individually addressable InGaAs/GaAs single-mode surface emitting laser diodes, 630 nm GaInP/GaAlInP surface-emitting laser diodes, and 1.3 micrometers InGaAsP/InP surface-emitting laser diodes grown on Si substrate.

Photonics activities at Sandia National Laboratories are founded on an extensive materials research program. In 1988, the Compound Semiconductor Research Laboratory was established at Sandia to bring together device and materials research and development, in support of Sandia's role in weapons technologies. Recently, industrial competitiveness has been added as a major mission for the national laboratories. As a result, present photonics programs are not only directed towards internal applications-driven projects, but are increasingly tied to the Department of Energy's Technology Transfer Initiatives, Cooperative Research and Development Agreements, and participation in partnerships and consortia. This evolution yields a full range of photonics programs, ranging from materials synthesis and device fabrication to packaging, test, and subsystem development. This paper presents an overview of Sandia's photonics-program directions, using three applications as examples.

We present in this paper the research status of polymer-based photonic integrated circuits (PICs) and their applications for VLSI optoelectronic interconnects. Demonstrated features of polymer-based PICs are delineated with GaAs and LiNbO₃ integrated photonic devices as references. These unique features, including longer interconnection length, larger phase modulation index, graded-index (GRIN) characteristic, massive fanout capability and cost- effectiveness, make the polymer-based PICs very attractive for an optoelectronically interconnected VLSI system. The usefulness of polymer-based PICs for VLSI optoelectronic interconnects relies on not only the system requirements but also the processing temperatures over which polymer-based photonic devices are fabricated and then assembled. Optical bus design rules are provided in this paper to optimize the interconnection length while maintaining low cross talk and maximum bus packing density. Optoelectronically interconnected inter-MCM (multi-chip module) and intra-MCM will be the future research trend of optoelectronic interconnects. Intra-board and backplane optoelectronic interconnects represent the major milestones for the realization of these schemes.

Optical channel waveguides with single-mode dimensions have been fabricated using a photodefinable polymer system based on the benzocyclobutene resin and a bisarylazide photo- crosslinking agent. This photo-polymer offers a simple technique for fabricating optical interconnects in multi-chip modules. The processing conditions and developer selection required for the fabrication of benzocyclobutene optical waveguides is presented. With the losses in the waveguide typically less than 1 dB/cm, this material system is suitable for use in a variety of optical interconnect problems.

We report on the use of di/tri acrylates in a photocurable polymer system for the fabrication of optical channel waveguides. The high degree of cross-linking in these materials improves the stability over linear systems. We have formulated resin mixtures to fabricate both single-mode and multimode waveguides at dimensions comparable to optical fibers to improve fiber-to- waveguide coupling. Results on refractive index tailoring as well as DSC, DMA, processing resolution, and optical loss are presented.

A bus based singlemode optical backplane interconnect using D-fibers provides a flexible and modular approach for high speed processing and switching systems for telecommunications applications. This paper describes the implementation of a bus based system in a rack format, using evanescent optical connector technology.

In this paper, a crosstalk model is developed to study the packing density and interconnect distance limitations of an optical interconnect system employing polymer-based single-mode bus arrays. The upper limit of channel packing density (1250 channels/cm at interconnect distance of 5 cm) is determined for the first time using the crosstalk model, in which channel cross-coupling among an infinite number of waveguides is considered. Computer simulations are provided together with the proven experimental results. It is shown that there is a threshold of channel separation due to channel cross-coupling, which results in a tradeoff between channel packing density and interconnect distance. Waveguide dimension closer to the cutoff boundary of second mode (E₁₂^X) is preferred for an optimum design.

Optical interconnects play an increasingly important role in high-performance computing and communications. Computer-aided design (CAD) tools are essential for performance analyses and component specifications for optical interconnects. This paper discusses circuit- and system-level models and simulation methods for optical interconnects consisting of optical devices such as laser diodes, photoreceivers, optical fibers, and other optoelectronic devices.

Wavelength division multiplexing (WDM) is attracting considerable interest in the field of fiber optic telecommunications since it provides the means to utilize the large optical bandwidth of optical fibers. A key issue to implementing a WDM system is the development of new lightwave components such as laser arrays that can transmit at predetermined optical frequencies, as well as discrete lasers that can be quickly switched between predetermined optical frequencies. In addition to transmitters, wavelength selective receivers and fast tunable photodetectors as well as passive wavelength multiplexers and routers are required. Photonic integrated circuits can potentially integrate several of these optical functions one a chip.

Commercially available polyimides (PI) have been evaluated in the form of a 20 X 20 micrometers waveguide on a silicon substrate with 6 micrometers quartz as undercladding. A Fabry- Perot laser diode (LD) has been aligned to the waveguide. Silicone elastomere (SiR) has been multi-purposely used for overcladding of the waveguide, for indexmatching between the waveguide and LD and for encapsulation of the LD. The optical characterization of the whole device has included measurements of optical output power as a function of drive current, and threshold current as a function of time. No statistically significant increase of threshold current has been noticed during the test period. It is shown that the optical loss spectrum of the waveguide over the wavelength interval of 0.6 - 1.6 micrometers is strongly dependent on the curing parameters of the PI.

Characterizing propagation losses in integrated optical structures is quite cumbersome and time consuming. Particularly for single-mode optical polymer channel waveguide devices that are butt-coupled, uncertainty of end facet preparation can add considerable error in estimated propagation losses. At COMSAT Laboratories, we have produced NLO polymer channel waveguides of buried and stripe designs by reactive ion etching and evaluated their loss performance by cutback and retro-reflection techniques. The first method, which is based on optical transmission in polished butt-coupled devices, is commonly used. The second method requires retro-reflection of the transmitted beam so that the input light beam (retro-reflected) is matched to the optical waveguide beam profile. This method has a higher accuracy because there is no need to correct for the mode-mismatch loss typical of the first method. Also, loss measured at different wavelengths can be used to distinguish true propagation and scattering losses contributed by structural imperfections in the channel waveguide sidewalls.

A CAD tool for the optical interconnects is developed and described. It is able to trace scalar or polarized electromagnetic fields propagating through complex optical waveguiding media or free space. The scattering and radiation at index discontinuities are considered and optical beams diverging from the waveguide axis may be simulated. The intra-board and inter-board optical interconnects are simulated and discussed.

Experimental results of 1-to-2 intra-plane and of 1-to-32 inter-plane v-shaped fanouts are delineated. Coupling efficiencies of 48% for surface-normal and of 45% for near-surface- normal inter-plane fanout beams are theoretically and experimentally confirmed. The influence of the angular fluctuation of a device having two multiplexed waveguide holograms with film thickness of 15 micrometers and index modulation of 0.04 is studied. The angle between the two grating vectors is determined to be less than 26 degree(s) to keep the near-surface-normal fanout beams.

Optical interconnects for advanced computers have been postulated for the past two decades to obtain performance and reliability improvements over existing electrical interconnects. Optical interconnects have the potential for extremely high bandwidth, immunity to electromagnetic interference, elimination of radiated emissions, and lower costs. To date, this potential has yet to be realized. The ever increasing clock rates and interconnect complexity associated with emerging computer device technology as well as the increased emphasis on massively parallel processing may serve to hasten the implementation of optical interconnects into computer systems. This paper discusses some of the issues associated with the implementation of optical interconnects in advanced computer systems and presents the status of the U.S. Navy optical backplane interconnect system (OBIS) program.

Free-space optical interconnection has the potential to provide upwards of a million data channels between planes of electronic circuits. This may result in the planar board and backplane structures of today giving away to 3-D stacks of wafers or multi-chip modules interconnected via channels running perpendicular to the processor planes, thereby eliminating much of the packaging overhead. Three-dimensional packaging is very appealing for tightly coupled fine-grained parallel computing where the need for massive numbers of interconnections is severely taxing the capabilities of the planar structures. This paper describes a coordinated effort by four research organizations to demonstrate an operational fine-grained parallel computer that achieves global connectivity through the use of free space optical interconnects.

Using optoelectronic interconnections in electronic systems offers interesting perspectives. In particular the ability to massively interconnect parallel electronic planes in free-space leads to systems with a much higher interconnectivity than would be possible using only electronic interconnections. This paper addresses the quantitative modeling of such future systems. Our technique is based on a modification of Rent's rule, which is well suited for evaluating optoelectronic architectures. It leads to a characterization of how to use optoelectronic interconnections and how much is expected to be gained from it. As a direct result we draw some preliminary conclusions on how to use optical interconnections in optoelectronic architectures.

Vertical-cavity surface-emitting lasers (VCSELs) can be integrated with heterojunction phototransistors (HPTs) and heterojunction bipolar transistors (HBTs) on the same wafer to form high speed optical and optoelectronic switches, respectively, that can be optically or electrically addressed. This permits the direct communication and transmission of data between distributed electronic processors through an optical switching network. The experimental demonstration of an integrated optoelectronic HBT/VCSEL switch combining a GaAs/AlGaAs heterojunction bipolar transistor (HBT) with a VCSEL is described, using the same epilayer structure upon which binary HPT/VCSEL optical switches are also built. The monolithic HBT/VCSEL switch has high current gain, low power dissipation, and a high optical to electrical conversion efficiency. Its modulation response has been measured and modeled.

The packing density of a highly parallel free-space multi-stage optical interconnect network involving arrays of vertical cavity surface-emitting lasers (VCSELs), microlenses, and photodetectors is analyzed for the first time, based on a crosstalk model involving the diffraction-induced crosstalk among pixels. Variations of channel packing density, interconnection distance, and optical transmission efficiency are evaluated to provide optimum design parameters for the arrays of VCSELs, microlenses, and photodetectors. It is shown that it is pivotal to optimize the photodetector diameter in such an optical interconnect network. Photodetector array misalignment effects on system performance are further investigated, providing both transverse and longitudinal alignment tolerance. Several experiments are also conducted to verify the theory developed herein.

Free-space optical interconnects represent a solution to the needs of future connection- intensive digital systems such as ATM switching systems, and massively parallel processing computer systems. These systems require the large board-to-board connectivity provided by an optical backplane created with 2-D arrays of passive, free-space, parallel optical channels (POCs) to optically interconnect the systems electronic printed circuit boards (PCBs) and/or multi-chip modules (MCMs). Such a backplane will be capable of supporting terabit/second aggregate capacities with conductivity levels on the order of 10,000 input/output channels per PCB. Currently, we are developing the optical and optomechanical technology required for demonstrating these terabit capacity free-space optical backplanes. Results to be reported include the optical interconnection of two 4 X 4 FET-SEED transceiver smart pixel arrays, each being mounted on a separate PCB. Optical, electrical, mechanical, and thermal issues are discussed, and extensions of these results to future backplane projects are described.

In this paper, we describe a novel approach for fabrication of low-cost optoelectronic modules for optical interconnect applications. The concept includes: (1) placement of optical and electrical components on a common substrate using a chip-first MCM structure to improve thermal handling capabilities, (2) fabrication of both optical and electrical interconnects using planar processes compatible to standard IC processes in manufacturing to reduce nonrecurring engineering costs, and (3) application of adaptive interconnect for device-to-waveguide alignment to reduce recurring packaging costs. Preliminary results on waveguide fabrication and modeling of adaptive interconnect are discussed in this paper.

We report a 1-D, 1 Gbit/sec, fully integrated 1-to-10 optical planar bus array. The optical bus is made out of a thin glass substrate in conjunction with a 1-D hologram array, integrated on the surface. Based on the dispersion relation, the angular misalignment can be used to determine the wavelength tolerance of the optical bus, which is a representation of its modulation bandwidth. Using the experimental results of the angular tolerance, which is determined to be 0.5 degree(s), it can be shown that a wavelength coverage of 42 nm is achievable when this optical bus is used. The corresponding frequency is 7.5 THz.

In order to fabricate practical free-space optical interconnect systems, a thorough understanding of the effect of optical misalignment on the power throughput of an optical link is required. Further, not only assembly tolerances (resulting in misalignment) but also component manufacturing tolerances that also introduce vignetting into the optical system need to be studied. We present a study of a wide variety of assembly and component manufacturing errors and their effect on the integrated power falling onto the detector for planar space variant optical systems. We also discuss the trends of the different misalignment sensitivities as the interconnect distance increases.

Optical interconnection networks have potential uses in parallel processing computers and photonic switching systems. This paper presents the topology of nonblocking omega network (NON) and studies the topological equivalence variety of NON with Benes network by the graph analysis method.

A general algorithm, the graph analysis method (GAM), to determine the topological equivalence of interconnection networks (INs) is presented. The concept of topological equivalence variety of INs is introduced. Topological equivalence variety of crossover networks with omega and banyan networks are studied by the GAM.