Free space optical interconnect has provided a promising solution to the effective signal links of the increasing density and complexity in very-large-scale/large-scale integrated circuits. It is getting less affordable if such a system fails just for one tiny physical defect. Our analysis on the potential optical-electrical link failure provides guidelines for future testing and reliable system design. The study of fault models starts by exploring the underlying physical malfunctioning of the opto-electrical components, and their impacts on the assembled systems. We map the physical defects of opto-electronic devices into their corresponding logic-level representation for higher level design consideration. This mapping is chosen for its compatibility and practicability with digital electronic system designs where automated design tools can expedite the design optimization and verification process.