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1 May 1994 Multiport backside-illuminated CCD imagers for high-frame-rate camera applications
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Two multiport, second-generation CCD imager designs have been fabricated and successfully tested. They are a 16-port 512 X 512 array and a 32-port 1024 X 1024 array. Both designs are back illuminated, have on-chip CDS, lateral blooming control, and use a split vertical frame transfer architecture with full frame storage. The 512 X 512 device has been operated at rates over 800 frames per second. The 1024 X 1024 device has been operated at rates over 300 frames per second. The major changes incorporated in the second-generation design are, reduction in gate length in the output area to give improved high-clock-rate performance, modified on-chip CDS circuitry for reduced noise, and optimized implants to improve performance of blooming control at lower clock amplitude. This paper discusses the imager design improvements and presents measured performance results at high and moderate frame rates. The design and performance of three moderate frame rate cameras are discussed.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter A. Levine, Donald J. Sauer, Fu-Lung Hseuh, Frank V. Shallcross, Gordon Charles Taylor, Grazyna M. Meray, John R. Tower, Lorna J. Harrison, and William B. Lawler "Multiport backside-illuminated CCD imagers for high-frame-rate camera applications", Proc. SPIE 2172, Charge-Coupled Devices and Solid State Optical Sensors IV, (1 May 1994);


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