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1 May 1994 Overview of parallel processing approaches to image and video compression
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Proceedings Volume 2186, Image and Video Compression; (1994) https://doi.org/10.1117/12.173920
Event: IS&T/SPIE 1994 International Symposium on Electronic Imaging: Science and Technology, 1994, San Jose, CA, United States
Abstract
In this paper we present an overview of techniques used to implement various image and video compression algorithms using parallel processing. Approaches used can largely be divided into four areas. The first is the use of special purpose architectures designed specifically for image and video compression. An example of this is the use of an array of DSP chips to implement a version of MPEG1. The second approach is the use of VLSI techniques. These include various chip sets for JPEG and MPEG1. The third approach is algorithm driven, in which the structure of the compression algorithm describes the architecture, e.g. pyramid algorithms. The fourth approach is the implementation of algorithms on high performance parallel computers. Examples of this approach are the use of a massively parallel computer such as the MasPar MP-1 or the use of a coarse-grained machine such as the Intel Touchstone Delta.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ke Shen, Gregory W. Cook, Leah H. Jamieson, and Edward J. Delp III "Overview of parallel processing approaches to image and video compression", Proc. SPIE 2186, Image and Video Compression, (1 May 1994); https://doi.org/10.1117/12.173920
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