2 May 1994 Parallel butterfly algorithm and VLSI architectures for image decorrelation
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We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the- art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favorably comparable to the JPEG baseline lossless image compression schemes. We also discuss the parallelization issues of the JPEG baseline standard still compression schemes and their difficulties.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tinku Acharya, Tinku Acharya, Amar Mukherjee, Amar Mukherjee, } "Parallel butterfly algorithm and VLSI architectures for image decorrelation", Proc. SPIE 2187, Digital Video Compression on Personal Computers: Algorithms and Technologies, (2 May 1994); doi: 10.1117/12.174967; https://doi.org/10.1117/12.174967

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