13 May 1994 Supporting early development of advanced high-performance logic with synchrotron orbital radiation lithography: a feasibility evaluation
Author Affiliations +
Abstract
The synchrotron x ray lithography (XRL) project described was conducted as a learning and feasibility vehicle for gate level lithography in support of IBM's most advanced CMOS logic programs. An electrically probable multilevel lithography test site was developed and characterized to exercise critical design, mask manufacture, alignment, exposure, and metrology issues in the 150 - 350 nm linewidth range. A fully capped silicided polysilicon gate stack was chosen for the electrical measurements in order to develop and demonstrate the XRL and related reactive ion etch process on a realistic, product-like substrate. This paper addresses test site design issues, elaborates on the mask manufacturing process, and presents SEM and electrical data from wafers processed at IBM's Advanced Semiconductor Technology Center. The data presented demonstrate the feasibility of supporting early device development and process integration with XRL and highlight the need for high resolution, defect free, proximity corrected masks to fully exploit the capabilities of x ray lithography.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lars W. Liebmann, Lars W. Liebmann, Andrew T.S. Pomerene, Andrew T.S. Pomerene, Daniel J. DeMay, Daniel J. DeMay, Angela C. Lamberti, Angela C. Lamberti, Thomas P. Donohue, Thomas P. Donohue, Joachim N. Burghartz, Joachim N. Burghartz, } "Supporting early development of advanced high-performance logic with synchrotron orbital radiation lithography: a feasibility evaluation", Proc. SPIE 2194, Electron-Beam, X-Ray, and Ion-Beam Submicrometer Lithographies for Manufacturing IV, (13 May 1994); doi: 10.1117/12.175816; https://doi.org/10.1117/12.175816
PROCEEDINGS
12 PAGES


SHARE
Back to Top